#include "qemu-timer.h"
#include "usb.h"
#include "pci.h"
-#include "devices.h"
#include "usb-ohci.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
//#define DEBUG_OHCI
/* Dump packet contents. */
uint32_t ctrl;
} OHCIPort;
-enum ohci_type {
- OHCI_TYPE_PCI,
- OHCI_TYPE_PXA,
- OHCI_TYPE_SM501,
-};
-
typedef struct {
USBBus bus;
qemu_irq irq;
- enum ohci_type type;
int mem;
int num_ports;
const char *name;
{
int dir;
size_t len = 0;
+#ifdef DEBUG_ISOCH
const char *str = NULL;
+#endif
int pid;
int ret;
int i;
dir = OHCI_BM(ed->flags, ED_D);
switch (dir) {
case OHCI_TD_DIR_IN:
+#ifdef DEBUG_ISOCH
str = "in";
+#endif
pid = USB_TOKEN_IN;
break;
case OHCI_TD_DIR_OUT:
+#ifdef DEBUG_ISOCH
str = "out";
+#endif
pid = USB_TOKEN_OUT;
break;
case OHCI_TD_DIR_SETUP:
+#ifdef DEBUG_ISOCH
str = "setup";
+#endif
pid = USB_TOKEN_SETUP;
break;
default:
{
int dir;
size_t len = 0;
+#ifdef DEBUG_PACKET
const char *str = NULL;
+#endif
int pid;
int ret;
int i;
switch (dir) {
case OHCI_TD_DIR_IN:
+#ifdef DEBUG_PACKET
str = "in";
+#endif
pid = USB_TOKEN_IN;
break;
case OHCI_TD_DIR_OUT:
+#ifdef DEBUG_PACKET
str = "out";
+#endif
pid = USB_TOKEN_OUT;
break;
case OHCI_TD_DIR_SETUP:
+#ifdef DEBUG_PACKET
str = "setup";
+#endif
pid = USB_TOKEN_SETUP;
break;
default:
flag_r = (td.flags & OHCI_TD_R) != 0;
#ifdef DEBUG_PACKET
DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
- addr, len, str, flag_r, td.cbp, td.be);
+ addr, (int64_t)len, str, flag_r, td.cbp, td.be);
if (len > 0 && dir != OHCI_TD_DIR_IN) {
DPRINTF(" data:");
static void ohci_process_lists(OHCIState *ohci, int completion)
{
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
- if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
- DPRINTF("usb-ohci: head %x, cur %x\n",
- ohci->ctrl_head, ohci->ctrl_cur);
+ if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
+ DPRINTF("usb-ohci: head %x, cur %x\n",
+ ohci->ctrl_head, ohci->ctrl_cur);
+ }
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
ohci->ctrl_cur = 0;
ohci->status &= ~OHCI_STATUS_CLF;
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
- if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
+ if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
+ }
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
return;
}
-static uint32_t ohci_mem_read_le(void *ptr, target_phys_addr_t addr)
+static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
{
OHCIState *ohci = ptr;
uint32_t retval;
+ addr &= 0xff;
+
/* Only aligned reads are allowed on OHCI */
if (addr & 3) {
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
retval = 0xffffffff;
}
}
- return retval;
-}
-
-static uint32_t ohci_mem_read_be(void *ptr, target_phys_addr_t addr)
-{
- uint32_t retval;
- retval = ohci_mem_read_le(ptr, addr);
- retval = bswap32(retval);
return retval;
}
-static void ohci_mem_write_le(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
{
OHCIState *ohci = ptr;
+ addr &= 0xff;
+
/* Only aligned reads are allowed on OHCI */
if (addr & 3) {
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
}
}
-static void ohci_mem_write_be(void *ptr, target_phys_addr_t addr, uint32_t val)
-{
- val = bswap32(val);
- ohci_mem_write_le(ptr, addr, val);
-}
-
/* Only dword reads are defined on OHCI register space */
-static CPUReadMemoryFunc * const ohci_readfn_be[3]={
- ohci_mem_read_be,
- ohci_mem_read_be,
- ohci_mem_read_be
+static CPUReadMemoryFunc * const ohci_readfn[3]={
+ ohci_mem_read,
+ ohci_mem_read,
+ ohci_mem_read
};
/* Only dword writes are defined on OHCI register space */
-static CPUWriteMemoryFunc * const ohci_writefn_be[3]={
- ohci_mem_write_be,
- ohci_mem_write_be,
- ohci_mem_write_be
+static CPUWriteMemoryFunc * const ohci_writefn[3]={
+ ohci_mem_write,
+ ohci_mem_write,
+ ohci_mem_write
};
-static CPUReadMemoryFunc * const ohci_readfn_le[3]={
- ohci_mem_read_le,
- ohci_mem_read_le,
- ohci_mem_read_le
-};
-
-static CPUWriteMemoryFunc * const ohci_writefn_le[3]={
- ohci_mem_write_le,
- ohci_mem_write_le,
- ohci_mem_write_le
+static USBPortOps ohci_port_ops = {
+ .attach = ohci_attach,
};
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
- int num_ports, int devfn,
- qemu_irq irq, enum ohci_type type,
- const char *name, uint32_t localmem_base,
- int be)
+ int num_ports, uint32_t localmem_base)
{
int i;
usb_frame_time, usb_bit_time);
}
- if (be) {
- ohci->mem = cpu_register_io_memory(ohci_readfn_be, ohci_writefn_be,
- ohci);
- } else {
- ohci->mem = cpu_register_io_memory(ohci_readfn_le, ohci_writefn_le,
- ohci);
- }
+ ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
+ DEVICE_LITTLE_ENDIAN);
ohci->localmem_base = localmem_base;
- ohci->name = name;
- ohci->irq = irq;
- ohci->type = type;
+ ohci->name = dev->info->name;
usb_bus_new(&ohci->bus, dev);
ohci->num_ports = num_ports;
for (i = 0; i < num_ports; i++) {
- usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, ohci_attach);
+ usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, NULL, &ohci_port_ops);
}
ohci->async_td = 0;
typedef struct {
PCIDevice pci_dev;
OHCIState state;
- uint32_t be;
} OHCIPCIState;
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
/* TODO: RST# value should be 0. */
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
- usb_ohci_init(&ohci->state, &dev->qdev, num_ports,
- ohci->pci_dev.devfn, ohci->pci_dev.irq[0],
- OHCI_TYPE_PCI, ohci->pci_dev.name, 0, ohci->be);
+ usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
+ ohci->state.irq = ohci->pci_dev.irq[0];
/* TODO: avoid cast below by using dev */
- pci_register_bar((struct PCIDevice *)ohci, 0, 256,
+ pci_register_bar(&ohci->pci_dev, 0, 256,
PCI_BASE_ADDRESS_SPACE_MEMORY, ohci_mapfunc);
return 0;
}
-void usb_ohci_init_pci(struct PCIBus *bus, int devfn, int be)
+void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
{
- PCIDevice *dev;
-
- dev = pci_create(bus, devfn, "pci-ohci");
- qdev_prop_set_uint32(&dev->qdev, "be", be);
- qdev_init_nofail(&dev->qdev);
+ pci_create_simple(bus, devfn, "pci-ohci");
}
-void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
- qemu_irq irq, int be)
-{
- OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
-
- usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq,
- OHCI_TYPE_PXA, "OHCI USB", 0, be);
-
- cpu_register_physical_memory(base, 0x1000, ohci->mem);
-}
+typedef struct {
+ SysBusDevice busdev;
+ OHCIState ohci;
+ uint32_t num_ports;
+ target_phys_addr_t dma_offset;
+} OHCISysBusState;
-void usb_ohci_init_sm501(uint32_t mmio_base, uint32_t localmem_base,
- int num_ports, int devfn, qemu_irq irq, int be)
+static int ohci_init_pxa(SysBusDevice *dev)
{
- OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
+ OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
- usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq,
- OHCI_TYPE_SM501, "OHCI USB", localmem_base, be);
+ usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
+ sysbus_init_irq(dev, &s->ohci.irq);
+ sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
- cpu_register_physical_memory(mmio_base, 0x1000, ohci->mem);
+ return 0;
}
-static PCIDeviceInfo ohci_info = {
+static PCIDeviceInfo ohci_pci_info = {
.qdev.name = "pci-ohci",
.qdev.desc = "Apple USB Controller",
.qdev.size = sizeof(OHCIPCIState),
.init = usb_ohci_initfn_pci,
- .qdev.props = (Property[]) {
- DEFINE_PROP_HEX32("be", OHCIPCIState, be, 0),
+};
+
+static SysBusDeviceInfo ohci_sysbus_info = {
+ .init = ohci_init_pxa,
+ .qdev.name = "sysbus-ohci",
+ .qdev.desc = "OHCI USB Controller",
+ .qdev.size = sizeof(OHCISysBusState),
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
+ DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
DEFINE_PROP_END_OF_LIST(),
}
};
static void ohci_register(void)
{
- pci_qdev_register(&ohci_info);
+ pci_qdev_register(&ohci_pci_info);
+ sysbus_register_withprop(&ohci_sysbus_info);
}
device_init(ohci_register);
projects / qemu.git / blobdiff