int vretr_start_line;
int vretr_end_line;
- int div2, sldiv2, dots;
+ int dots;
+#if 0
+ int div2, sldiv2;
+#endif
int clocking_mode;
int clock_sel;
const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
vretr_end_line = s->cr[0x11] & 0xf;
- div2 = (s->cr[0x17] >> 2) & 1;
- sldiv2 = (s->cr[0x17] >> 3) & 1;
clocking_mode = (s->sr[0x01] >> 3) & 1;
clock_sel = (s->msr >> 2) & 3;
r->htotal = htotal_chars;
#if 0
+ div2 = (s->cr[0x17] >> 2) & 1;
+ sldiv2 = (s->cr[0x17] >> 3) & 1;
printf (
"hz=%f\n"
"htotal = %d\n"
"clocking_mode = %d\n"
"clock_sel = %d %d\n"
"dots = %d\n"
- "ticks/char = %lld\n"
+ "ticks/char = %" PRId64 "\n"
"\n",
(double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
htotal_chars,
int cur_line, cur_line_char, cur_char;
int64_t cur_tick;
- cur_tick = qemu_get_clock(vm_clock);
+ cur_tick = qemu_get_clock_ns(vm_clock);
cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
cur_line = cur_char / r->htotal;
VGACommonState *s = opaque;
uint32_t val;
- if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
+ if (s->vbe_index < VBE_DISPI_INDEX_NB) {
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
switch(s->vbe_index) {
/* XXX: do not hardcode ? */
} else {
val = s->vbe_regs[s->vbe_index];
}
+ } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
+ val = s->vram_size / (64 * 1024);
} else {
val = 0;
}
#endif
/* called for accesses between 0xa0000 and 0xc0000 */
-uint32_t vga_mem_readb(void *opaque, a_target_phys_addr addr)
+uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
{
VGACommonState *s = opaque;
int memory_map_mode, plane;
return ret;
}
-static uint32_t vga_mem_readw(void *opaque, a_target_phys_addr addr)
+static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = vga_mem_readb(opaque, addr) << 8;
- v |= vga_mem_readb(opaque, addr + 1);
-#else
v = vga_mem_readb(opaque, addr);
v |= vga_mem_readb(opaque, addr + 1) << 8;
-#endif
return v;
}
-static uint32_t vga_mem_readl(void *opaque, a_target_phys_addr addr)
+static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = vga_mem_readb(opaque, addr) << 24;
- v |= vga_mem_readb(opaque, addr + 1) << 16;
- v |= vga_mem_readb(opaque, addr + 2) << 8;
- v |= vga_mem_readb(opaque, addr + 3);
-#else
v = vga_mem_readb(opaque, addr);
v |= vga_mem_readb(opaque, addr + 1) << 8;
v |= vga_mem_readb(opaque, addr + 2) << 16;
v |= vga_mem_readb(opaque, addr + 3) << 24;
-#endif
return v;
}
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
+void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
VGACommonState *s = opaque;
int memory_map_mode, plane, write_mode, b, func_select, mask;
}
}
-static void vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
- vga_mem_writeb(opaque, addr + 1, val & 0xff);
-#else
vga_mem_writeb(opaque, addr, val & 0xff);
vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-#endif
}
-static void vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
+static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
- vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
- vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
- vga_mem_writeb(opaque, addr + 3, val & 0xff);
-#else
vga_mem_writeb(opaque, addr, val & 0xff);
vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-#endif
}
typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
}
}
-static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
+static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
vga_draw_glyph8_8,
vga_draw_glyph8_16,
vga_draw_glyph8_16,
vga_draw_glyph8_16,
};
-static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
+static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
vga_draw_glyph16_8,
vga_draw_glyph16_16,
vga_draw_glyph16_16,
vga_draw_glyph16_16,
};
-static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
+static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
vga_draw_glyph9_8,
vga_draw_glyph9_16,
vga_draw_glyph9_16,
typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
-static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
+static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
rgb_to_pixel8_dup,
rgb_to_pixel15_dup,
rgb_to_pixel16_dup,
static void vga_draw_text(VGACommonState *s, int full_update)
{
int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
- int cx_min, cx_max, linesize, x_incr;
+ int cx_min, cx_max, linesize, x_incr, line, line1;
uint32_t offset, fgcol, bgcol, v, cursor_offset;
- uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
+ uint8_t *d1, *d, *src, *dest, *cursor_ptr;
const uint8_t *font_ptr, *font_base[2];
int dup9, line_offset, depth_index;
uint32_t *palette;
full_update |= update_basic_params(s);
line_offset = s->line_offset;
- s1 = s->vram_ptr + (s->start_addr * 4);
vga_get_text_resolution(s, &width, &height, &cw, &cheight);
- x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
if ((height * width) > CH_ATTR_SIZE) {
/* better than nothing: exit if transient size is too big */
return;
dest = ds_get_data(s->ds);
linesize = ds_get_linesize(s->ds);
ch_attr_ptr = s->last_ch_attr;
+ line = 0;
+ offset = s->start_addr * 4;
for(cy = 0; cy < height; cy++) {
d1 = dest;
- src = s1;
+ src = s->vram_ptr + offset;
cx_min = width;
cx_max = -1;
for(cx = 0; cx < width; cx++) {
(cx_max - cx_min + 1) * cw, cheight);
}
dest += linesize * cheight;
- s1 += line_offset;
+ line1 = line + cheight;
+ offset += line_offset;
+ if (line < s->line_compare && line1 >= s->line_compare) {
+ offset = 0;
+ }
+ line = line1;
}
}
VGA_DRAW_LINE_NB,
};
-static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
+static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
vga_draw_line2_8,
vga_draw_line2_16,
vga_draw_line2_16,
cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
}
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_sync_dirty_bitmap(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ VBE_DISPI_LFB_PHYSICAL_ADDRESS + s->vram_size);
+ }
+#endif
+
+}
+
+void vga_dirty_log_start(VGACommonState *s)
+{
+ if (s->map_addr) {
+ cpu_physical_log_start(s->map_addr, s->map_end - s->map_addr);
+ }
+
+ if (s->lfb_vram_mapped) {
+ cpu_physical_log_start(isa_mem_base + 0xa0000, 0x8000);
+ cpu_physical_log_start(isa_mem_base + 0xa8000, 0x8000);
+ }
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_log_start(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
+ }
+#endif
+}
+
+void vga_dirty_log_stop(VGACommonState *s)
+{
+ if (s->map_addr) {
+ cpu_physical_log_stop(s->map_addr, s->map_end - s->map_addr);
+ }
+
+ if (s->lfb_vram_mapped) {
+ cpu_physical_log_stop(isa_mem_base + 0xa0000, 0x8000);
+ cpu_physical_log_stop(isa_mem_base + 0xa8000, 0x8000);
+ }
+
+#ifdef CONFIG_BOCHS_VBE
+ if (s->vbe_mapped) {
+ cpu_physical_log_stop(VBE_DISPI_LFB_PHYSICAL_ADDRESS, s->vram_size);
+ }
+#endif
+}
+
+void vga_dirty_log_restart(VGACommonState *s)
+{
+ vga_dirty_log_stop(s);
+ vga_dirty_log_start(s);
}
/*
{
int y1, y, update, linesize, y_start, double_scan, mask, depth;
int width, height, shift_control, line_offset, bwidth, bits;
- a_ram_addr page0, page1, page_min, page_max;
+ ram_addr_t page0, page1, page_min, page_max;
int disp_width, multi_scan, multi_run;
uint8_t *d;
uint32_t v, addr1, addr;
if (ds_get_bits_per_pixel(s->ds) == 0) {
/* nothing to do */
} else {
- full_update = s->full_update;
- s->full_update = 0;
+ full_update = 0;
if (!(s->ar_index & 0x20)) {
graphic_mode = GMODE_BLANK;
} else {
{
VGACommonState *s = opaque;
- s->full_update = 1;
+ s->last_width = -1;
+ s->last_height = -1;
}
void vga_common_reset(VGACommonState *s)
s->map_addr = 0;
s->map_end = 0;
s->lfb_vram_mapped = 0;
- s->bios_offset = 0;
- s->bios_size = 0;
s->sr_index = 0;
memset(s->sr, '\0', sizeof(s->sr));
s->gr_index = 0;
#ifdef CONFIG_BOCHS_VBE
s->vbe_index = 0;
memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
- s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
+ s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
s->vbe_start_addr = 0;
s->vbe_line_offset = 0;
s->vbe_bank_mask = (s->vram_size >> 16) - 1;
((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
/* relay text rendering to the display driver
* instead of doing a full vga_update_display() */
-static void vga_update_text(void *opaque, a_console_ch *chardata)
+static void vga_update_text(void *opaque, console_ch_t *chardata)
{
VGACommonState *s = opaque;
int graphic_mode, i, cursor_offset, cursor_visible;
int cw, cheight, width, height, size, c_min, c_max;
uint32_t *src;
- a_console_ch *dst, val;
+ console_ch_t *dst, val;
char msg_buffer[80];
int full_update = 0;
if (full_update) {
for (i = 0; i < size; src ++, dst ++, i ++)
- console_write_ch(dst, VMEM2CHTYPE(*src));
+ console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
dpy_update(s->ds, 0, 0, width, height);
} else {
c_max = 0;
for (i = 0; i < size; src ++, dst ++, i ++) {
- console_write_ch(&val, VMEM2CHTYPE(*src));
+ console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
if (*dst != val) {
*dst = val;
c_max = i;
}
c_min = i;
for (; i < size; src ++, dst ++, i ++) {
- console_write_ch(&val, VMEM2CHTYPE(*src));
+ console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
if (*dst != val) {
*dst = val;
c_max = i;
vga_mem_writel,
};
-void vga_common_save(QEMUFile *f, void *opaque)
+static int vga_common_post_load(void *opaque, int version_id)
{
VGACommonState *s = opaque;
- int i;
-
- qemu_put_be32s(f, &s->latch);
- qemu_put_8s(f, &s->sr_index);
- qemu_put_buffer(f, s->sr, 8);
- qemu_put_8s(f, &s->gr_index);
- qemu_put_buffer(f, s->gr, 16);
- qemu_put_8s(f, &s->ar_index);
- qemu_put_buffer(f, s->ar, 21);
- qemu_put_be32(f, s->ar_flip_flop);
- qemu_put_8s(f, &s->cr_index);
- qemu_put_buffer(f, s->cr, 256);
- qemu_put_8s(f, &s->msr);
- qemu_put_8s(f, &s->fcr);
- qemu_put_byte(f, s->st00);
- qemu_put_8s(f, &s->st01);
-
- qemu_put_8s(f, &s->dac_state);
- qemu_put_8s(f, &s->dac_sub_index);
- qemu_put_8s(f, &s->dac_read_index);
- qemu_put_8s(f, &s->dac_write_index);
- qemu_put_buffer(f, s->dac_cache, 3);
- qemu_put_buffer(f, s->palette, 768);
-
- qemu_put_be32(f, s->bank_offset);
-#ifdef CONFIG_BOCHS_VBE
- qemu_put_byte(f, 1);
- qemu_put_be16s(f, &s->vbe_index);
- for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
- qemu_put_be16s(f, &s->vbe_regs[i]);
- qemu_put_be32s(f, &s->vbe_start_addr);
- qemu_put_be32s(f, &s->vbe_line_offset);
- qemu_put_be32s(f, &s->vbe_bank_mask);
-#else
- qemu_put_byte(f, 0);
-#endif
-}
-
-int vga_common_load(QEMUFile *f, void *opaque, int version_id)
-{
- VGACommonState *s = opaque;
- int is_vbe, i;
-
- if (version_id > 2)
- return -EINVAL;
-
- qemu_get_be32s(f, &s->latch);
- qemu_get_8s(f, &s->sr_index);
- qemu_get_buffer(f, s->sr, 8);
- qemu_get_8s(f, &s->gr_index);
- qemu_get_buffer(f, s->gr, 16);
- qemu_get_8s(f, &s->ar_index);
- qemu_get_buffer(f, s->ar, 21);
- s->ar_flip_flop=qemu_get_be32(f);
- qemu_get_8s(f, &s->cr_index);
- qemu_get_buffer(f, s->cr, 256);
- qemu_get_8s(f, &s->msr);
- qemu_get_8s(f, &s->fcr);
- qemu_get_8s(f, &s->st00);
- qemu_get_8s(f, &s->st01);
-
- qemu_get_8s(f, &s->dac_state);
- qemu_get_8s(f, &s->dac_sub_index);
- qemu_get_8s(f, &s->dac_read_index);
- qemu_get_8s(f, &s->dac_write_index);
- qemu_get_buffer(f, s->dac_cache, 3);
- qemu_get_buffer(f, s->palette, 768);
-
- s->bank_offset=qemu_get_be32(f);
- is_vbe = qemu_get_byte(f);
-#ifdef CONFIG_BOCHS_VBE
- if (!is_vbe)
- return -EINVAL;
- qemu_get_be16s(f, &s->vbe_index);
- for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
- qemu_get_be16s(f, &s->vbe_regs[i]);
- qemu_get_be32s(f, &s->vbe_start_addr);
- qemu_get_be32s(f, &s->vbe_line_offset);
- qemu_get_be32s(f, &s->vbe_bank_mask);
-#else
- if (is_vbe)
- return -EINVAL;
-#endif
/* force refresh */
s->graphic_mode = -1;
return 0;
}
+const VMStateDescription vmstate_vga_common = {
+ .name = "vga",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .post_load = vga_common_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(latch, VGACommonState),
+ VMSTATE_UINT8(sr_index, VGACommonState),
+ VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
+ VMSTATE_UINT8(gr_index, VGACommonState),
+ VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
+ VMSTATE_UINT8(ar_index, VGACommonState),
+ VMSTATE_BUFFER(ar, VGACommonState),
+ VMSTATE_INT32(ar_flip_flop, VGACommonState),
+ VMSTATE_UINT8(cr_index, VGACommonState),
+ VMSTATE_BUFFER(cr, VGACommonState),
+ VMSTATE_UINT8(msr, VGACommonState),
+ VMSTATE_UINT8(fcr, VGACommonState),
+ VMSTATE_UINT8(st00, VGACommonState),
+ VMSTATE_UINT8(st01, VGACommonState),
+
+ VMSTATE_UINT8(dac_state, VGACommonState),
+ VMSTATE_UINT8(dac_sub_index, VGACommonState),
+ VMSTATE_UINT8(dac_read_index, VGACommonState),
+ VMSTATE_UINT8(dac_write_index, VGACommonState),
+ VMSTATE_BUFFER(dac_cache, VGACommonState),
+ VMSTATE_BUFFER(palette, VGACommonState),
+
+ VMSTATE_INT32(bank_offset, VGACommonState),
+ VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
+#ifdef CONFIG_BOCHS_VBE
+ VMSTATE_UINT16(vbe_index, VGACommonState),
+ VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
+ VMSTATE_UINT32(vbe_start_addr, VGACommonState),
+ VMSTATE_UINT32(vbe_line_offset, VGACommonState),
+ VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
+#endif
+ VMSTATE_END_OF_LIST()
+ }
+};
+
void vga_common_init(VGACommonState *s, int vga_ram_size)
{
int i, j, v, b;
expand4to8[i] = v;
}
- s->vram_offset = qemu_ram_alloc(vga_ram_size);
+#ifdef CONFIG_BOCHS_VBE
+ s->is_vbe_vmstate = 1;
+#else
+ s->is_vbe_vmstate = 0;
+#endif
+ s->vram_offset = qemu_ram_alloc(NULL, "vga.vram", vga_ram_size);
s->vram_ptr = qemu_get_ram_ptr(s->vram_offset);
s->vram_size = vga_ram_size;
s->get_bpp = vga_get_bpp;
s->update_retrace_info = vga_precise_update_retrace_info;
break;
}
- vga_reset(s);
}
/* used by both ISA and PCI */
-void vga_init(VGACommonState *s)
+int vga_init_io(VGACommonState *s)
{
- int vga_io_memory;
-
- qemu_register_reset(vga_reset, s);
-
register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
- s->bank_offset = 0;
#ifdef CONFIG_BOCHS_VBE
#if defined (TARGET_I386)
register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
-
- /* old Bochs IO ports */
- register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
- register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
-
- register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
- register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
#else
register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
#endif
#endif /* CONFIG_BOCHS_VBE */
- vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
+ return cpu_register_io_memory(vga_mem_read, vga_mem_write, s,
+ DEVICE_LITTLE_ENDIAN);
+}
+
+void vga_init(VGACommonState *s)
+{
+ int vga_io_memory;
+
+ qemu_register_reset(vga_reset, s);
+
+ s->bank_offset = 0;
+
+ vga_io_memory = vga_init_io(s);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
}
+void vga_init_vbe(VGACommonState *s)
+{
+#ifdef CONFIG_BOCHS_VBE
+ /* XXX: use optimized standard vga accesses */
+ cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ VGA_RAM_SIZE, s->vram_offset);
+ s->vbe_mapped = 1;
+#endif
+}
/********************************************************/
/* vga screen dump */
uint32_t v;
int y, x;
uint8_t r, g, b;
+ int ret;
+ char *linebuf, *pbuf;
f = fopen(filename, "wb");
if (!f)
return -1;
fprintf(f, "P6\n%d %d\n%d\n",
ds->width, ds->height, 255);
+ linebuf = qemu_malloc(ds->width * 3);
d1 = ds->data;
for(y = 0; y < ds->height; y++) {
d = d1;
+ pbuf = linebuf;
for(x = 0; x < ds->width; x++) {
if (ds->pf.bits_per_pixel == 32)
v = *(uint32_t *)d;
(ds->pf.gmax + 1);
b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
(ds->pf.bmax + 1);
- fputc(r, f);
- fputc(g, f);
- fputc(b, f);
+ *pbuf++ = r;
+ *pbuf++ = g;
+ *pbuf++ = b;
d += ds->pf.bytes_per_pixel;
}
d1 += ds->linesize;
+ ret = fwrite(linebuf, 1, pbuf - linebuf, f);
+ (void)ret;
}
+ qemu_free(linebuf);
fclose(f);
return 0;
}
projects / qemu.git / blobdiff