struct XilinxAXIDMA {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t freqhz;
void *dmach;
stream_update_irq(s);
}
-static uint32_t axidma_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct XilinxAXIDMA *d = opaque;
struct AXIStream *s;
}
-static void
-axidma_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void axidma_write(void *opaque, target_phys_addr_t addr,
+ uint64_t value, unsigned size)
{
struct XilinxAXIDMA *d = opaque;
struct AXIStream *s;
stream_update_irq(s);
}
-static CPUReadMemoryFunc * const axidma_read[] = {
- &axidma_readl,
- &axidma_readl,
- &axidma_readl,
-};
-
-static CPUWriteMemoryFunc * const axidma_write[] = {
- &axidma_writel,
- &axidma_writel,
- &axidma_writel,
+static const MemoryRegionOps axidma_ops = {
+ .read = axidma_read,
+ .write = axidma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int xilinx_axidma_init(SysBusDevice *dev)
{
struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev);
- int axidma_regs;
int i;
sysbus_init_irq(dev, &s->streams[1].irq);
xlx_dma_connect_dma(s->dmach, s, axidma_push);
- axidma_regs = cpu_register_io_memory(axidma_read, axidma_write, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, R_MAX * 4 * 2, axidma_regs);
+ memory_region_init_io(&s->iomem, &axidma_ops, s,
+ "axidma", R_MAX * 4 * 2);
+ sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < 2; i++) {
stream_reset(&s->streams[i]);