* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "hw.h"
-#include "qemu-timer.h"
-#include "sysbus.h"
-#include "sysemu.h"
+#include "hw/hw.h"
+#include "qemu/timer.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
#ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
#define DB_PRINT(...) do { \
typedef enum {
PSS,
DDDR,
- DMAC,
+ DMAC = 3,
USB,
GEM,
SDIO,
{
int i;
ZynqSLCRState *s =
- FROM_SYSBUS(ZynqSLCRState, sysbus_from_qdev(d));
+ FROM_SYSBUS(ZynqSLCRState, SYS_BUS_DEVICE(d));
DB_PRINT("RESET\n");
}
static inline uint32_t zynq_slcr_read_imp(void *opaque,
- target_phys_addr_t offset)
+ hwaddr offset)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
}
}
-static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset,
+static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t ret = zynq_slcr_read_imp(opaque, offset);
- DB_PRINT("addr: %08x data: %08x\n", offset, ret);
+ DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
return ret;
}
-static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
+static void zynq_slcr_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
- DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val);
+ DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val);
switch (offset) {
case 0x00: /* SCL */
break;
default:
bad_reg:
- DB_PRINT("Bad register write %x <= %08x\n", (int)offset, val);
+ DB_PRINT("Bad register write %x <= %08x\n", (int)offset,
+ (unsigned)val);
}
} else {
DB_PRINT("SCLR registers are locked. Unlock them first\n");
dc->reset = zynq_slcr_reset;
}
-static TypeInfo zynq_slcr_info = {
+static const TypeInfo zynq_slcr_info = {
.class_init = zynq_slcr_class_init,
.name = "xilinx,zynq_slcr",
.parent = TYPE_SYS_BUS_DEVICE,