} QEMU_PACKED;
typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+struct AcpiMadtProcessorX2Apic {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t x2apic_id; /* Processor's local x2APIC ID */
+ uint32_t flags;
+ uint32_t uid; /* Processor object _UID */
+} QEMU_PACKED;
+typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic;
+
+struct AcpiMadtLocalX2ApicNmi {
+ ACPI_SUB_HEADER_DEF
+ uint16_t flags; /* MPS INTI flags */
+ uint32_t uid; /* Processor object _UID */
+ uint8_t lint; /* Local APIC LINT# */
+ uint8_t reserved[3]; /* Local APIC LINT# */
+} QEMU_PACKED;
+typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi;
+
struct AcpiMadtGenericInterrupt {
ACPI_SUB_HEADER_DEF
uint16_t reserved;
} QEMU_PACKED;
typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
+struct AcpiSratProcessorX2ApicAffinity {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t proximity_domain;
+ uint32_t x2apic_id;
+ uint32_t flags;
+ uint32_t clk_domain;
+ uint32_t reserved2;
+} QEMU_PACKED;
+typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity;
+
struct AcpiSratMemoryAffinity
{
ACPI_SUB_HEADER_DEF
/* Masks for Flags field above */
#define ACPI_DMAR_INCLUDE_PCI_ALL 1
+/*
+ * Input Output Remapping Table (IORT)
+ * Conforms to "IO Remapping Table System Software on ARM Platforms",
+ * Document number: ARM DEN 0049B, October 2015
+ */
+
+struct AcpiIortTable {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ uint32_t node_count;
+ uint32_t node_offset;
+ uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiIortTable AcpiIortTable;
+
+/*
+ * IORT node types
+ */
+
+#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
+ uint8_t type; \
+ uint16_t length; \
+ uint8_t revision; \
+ uint32_t reserved; \
+ uint32_t mapping_count; \
+ uint32_t mapping_offset;
+
+/* Values for node Type above */
+enum {
+ ACPI_IORT_NODE_ITS_GROUP = 0x00,
+ ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
+ ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
+ ACPI_IORT_NODE_SMMU = 0x03,
+ ACPI_IORT_NODE_SMMU_V3 = 0x04
+};
+
+struct AcpiIortIdMapping {
+ uint32_t input_base;
+ uint32_t id_count;
+ uint32_t output_base;
+ uint32_t output_reference;
+ uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiIortIdMapping AcpiIortIdMapping;
+
+struct AcpiIortMemoryAccess {
+ uint32_t cache_coherency;
+ uint8_t hints;
+ uint16_t reserved;
+ uint8_t memory_flags;
+} QEMU_PACKED;
+typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
+
+struct AcpiIortItsGroup {
+ ACPI_IORT_NODE_HEADER_DEF
+ uint32_t its_count;
+ uint32_t identifiers[0];
+} QEMU_PACKED;
+typedef struct AcpiIortItsGroup AcpiIortItsGroup;
+
+struct AcpiIortRC {
+ ACPI_IORT_NODE_HEADER_DEF
+ AcpiIortMemoryAccess memory_properties;
+ uint32_t ats_attribute;
+ uint32_t pci_segment_number;
+ AcpiIortIdMapping id_mapping_array[0];
+} QEMU_PACKED;
+typedef struct AcpiIortRC AcpiIortRC;
+
#endif