Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

x86 and CPU queue, 2016-10-24

x2APIC support to APIC code, cpu_exec_init() refactor on all
architectures, and other x86 changes.

# gpg: Signature made Mon 24 Oct 2016 20:51:14 BST
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-pull-request:
  exec: call cpu_exec_exit() from a CPU unrealize common function
  exec: move cpu_exec_init() calls to realize functions
  exec: split cpu_exec_init()
  pc: q35: Bump max_cpus to 288
  pc: Require IRQ remapping and EIM if there could be x2APIC CPUs
  pc: Add 'etc/boot-cpus' fw_cfg file for machine with more than 255 CPUs
  Increase MAX_CPUMASK_BITS from 255 to 288
  pc: Clarify FW_CFG_MAX_CPUS usage comment
  pc: kvm_apic: Pass APIC ID depending on xAPIC/x2APIC mode
  pc: apic_common: Reset APIC ID to initial ID when switching into x2APIC mode
  pc: apic_common: Restore APIC ID to initial ID on reset
  pc: apic_common: Extend APIC ID property to 32bit
  pc: Leave max apic_id_limit only in legacy cpu hotplug code
  acpi: cphp: Force switch to modern cpu hotplug if APIC ID > 254
  pc: acpi: x2APIC support for SRAT table
  pc: acpi: x2APIC support for MADT table and _MAT method

Conflicts:
	target-arm/cpu.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --cc exec.c
Simple merge

diff --cc hw/arm/virt.c
Simple merge

diff --cc include/hw/acpi/acpi-defs.h
Simple merge

diff --cc target-arm/cpu.c
index c94a3245401eea1db82d40ee7c0e2d9b716376f4,fb272a86c1505611c148b4bbd323280303774d21..2439ca57d0000faf0dfcfe7283ab9fda97c1ddc2
--- 1/target-arm/cpu.c
--- 2/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@@ -576,7 -563,13 +563,14 @@@ static void arm_cpu_realizefn(DeviceSta
      ARMCPU *cpu = ARM_CPU(dev);
      ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
      CPUARMState *env = &cpu->env;
 +    int pagebits;
+     Error *local_err = NULL;
+ 
+     cpu_exec_realizefn(cs, &local_err);
+     if (local_err != NULL) {
+         error_propagate(errp, local_err);
+         return;
+     }
  
      /* Some features automatically imply others: */
      if (arm_feature(env, ARM_FEATURE_V8)) {
@@@ -632,29 -625,17 +626,40 @@@
          set_feature(env, ARM_FEATURE_THUMB_DSP);
      }
  
 +    if (arm_feature(env, ARM_FEATURE_V7) &&
 +        !arm_feature(env, ARM_FEATURE_M) &&
 +        !arm_feature(env, ARM_FEATURE_MPU)) {
 +        /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 +         * can use 4K pages.
 +         */
 +        pagebits = 12;
 +    } else {
 +        /* For CPUs which might have tiny 1K pages, or which have an
 +         * MPU and might have small region sizes, stick with 1K pages.
 +         */
 +        pagebits = 10;
 +    }
 +    if (!set_preferred_target_page_bits(pagebits)) {
 +        /* This can only ever happen for hotplugging a CPU, or if
 +         * the board code incorrectly creates a CPU which it has
 +         * promised via minimum_page_size that it will not.
 +         */
 +        error_setg(errp, "This CPU requires a smaller page size than the "
 +                   "system is using");
 +        return;
 +    }
 +
+     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
+      * We don't support setting cluster ID ([16..23]) (known as Aff2
+      * in later ARM ARM versions), or any of the higher affinity level fields,
+      * so these bits always RAZ.
+      */
+     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
+         uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
+         uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
+         cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
+     }
+ 
      if (cpu->reset_hivecs) {
              cpu->reset_sctlr |= (1 << 13);
      }