*/
#include "ioport.h"
+#include "trace.h"
/***********************************************************/
/* IO Port */
//#define DEBUG_UNUSED_IOPORT
//#define DEBUG_IOPORT
+#ifdef DEBUG_UNUSED_IOPORT
+# define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
+#else
+# define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
+#endif
+
#ifdef DEBUG_IOPORT
# define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
#else
static uint32_t ioport_read(int index, uint32_t address)
{
- static IOPortReadFunc *default_func[3] = {
+ static IOPortReadFunc * const default_func[3] = {
default_ioport_readb,
default_ioport_readw,
default_ioport_readl
static void ioport_write(int index, uint32_t address, uint32_t data)
{
- static IOPortWriteFunc *default_func[3] = {
+ static IOPortWriteFunc * const default_func[3] = {
default_ioport_writeb,
default_ioport_writew,
default_ioport_writel
static uint32_t default_ioport_readb(void *opaque, uint32_t address)
{
-#ifdef DEBUG_UNUSED_IOPORT
- fprintf(stderr, "unused inb: port=0x%04x\n", address);
-#endif
+ LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
return 0xff;
}
static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
{
-#ifdef DEBUG_UNUSED_IOPORT
- fprintf(stderr, "unused outb: port=0x%04x data=0x%02x\n", address, data);
-#endif
+ LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
+ address, data);
}
/* default is to make two byte accesses */
static uint32_t default_ioport_readl(void *opaque, uint32_t address)
{
-#ifdef DEBUG_UNUSED_IOPORT
- fprintf(stderr, "unused inl: port=0x%04x\n", address);
-#endif
+ LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
return 0xffffffff;
}
static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
{
-#ifdef DEBUG_UNUSED_IOPORT
- fprintf(stderr, "unused outl: port=0x%04x data=0x%02x\n", address, data);
-#endif
+ LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
+ address, data);
}
static int ioport_bsize(int size, int *bsize)
}
/* size is the word size in byte */
-int register_ioport_read(int start, int length, int size,
+int register_ioport_read(pio_addr_t start, int length, int size,
IOPortReadFunc *func, void *opaque)
{
int i, bsize;
for(i = start; i < start + length; i += size) {
ioport_read_table[bsize][i] = func;
if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
- hw_error("register_ioport_read: invalid opaque");
+ hw_error("register_ioport_read: invalid opaque for address 0x%x",
+ i);
ioport_opaque[i] = opaque;
}
return 0;
}
/* size is the word size in byte */
-int register_ioport_write(int start, int length, int size,
+int register_ioport_write(pio_addr_t start, int length, int size,
IOPortWriteFunc *func, void *opaque)
{
int i, bsize;
for(i = start; i < start + length; i += size) {
ioport_write_table[bsize][i] = func;
if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
- hw_error("register_ioport_write: invalid opaque");
+ hw_error("register_ioport_write: invalid opaque for address 0x%x",
+ i);
ioport_opaque[i] = opaque;
}
return 0;
}
-void isa_unassign_ioport(int start, int length)
+static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
+{
+ IORange *ioport = opaque;
+ uint64_t data;
+
+ ioport->ops->read(ioport, addr - ioport->base, 1, &data);
+ return data;
+}
+
+static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
+{
+ IORange *ioport = opaque;
+ uint64_t data;
+
+ ioport->ops->read(ioport, addr - ioport->base, 2, &data);
+ return data;
+}
+
+static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
+{
+ IORange *ioport = opaque;
+ uint64_t data;
+
+ ioport->ops->read(ioport, addr - ioport->base, 4, &data);
+ return data;
+}
+
+static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
+{
+ IORange *ioport = opaque;
+
+ ioport->ops->write(ioport, addr - ioport->base, 1, data);
+}
+
+static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
+{
+ IORange *ioport = opaque;
+
+ ioport->ops->write(ioport, addr - ioport->base, 2, data);
+}
+
+static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
+{
+ IORange *ioport = opaque;
+
+ ioport->ops->write(ioport, addr - ioport->base, 4, data);
+}
+
+void ioport_register(IORange *ioport)
+{
+ register_ioport_read(ioport->base, ioport->len, 1,
+ ioport_readb_thunk, ioport);
+ register_ioport_read(ioport->base, ioport->len, 2,
+ ioport_readw_thunk, ioport);
+ register_ioport_read(ioport->base, ioport->len, 4,
+ ioport_readl_thunk, ioport);
+ register_ioport_write(ioport->base, ioport->len, 1,
+ ioport_writeb_thunk, ioport);
+ register_ioport_write(ioport->base, ioport->len, 2,
+ ioport_writew_thunk, ioport);
+ register_ioport_write(ioport->base, ioport->len, 4,
+ ioport_writel_thunk, ioport);
+}
+
+void isa_unassign_ioport(pio_addr_t start, int length)
{
int i;
for(i = start; i < start + length; i++) {
- ioport_read_table[0][i] = default_ioport_readb;
- ioport_read_table[1][i] = default_ioport_readw;
- ioport_read_table[2][i] = default_ioport_readl;
+ ioport_read_table[0][i] = NULL;
+ ioport_read_table[1][i] = NULL;
+ ioport_read_table[2][i] = NULL;
- ioport_write_table[0][i] = default_ioport_writeb;
- ioport_write_table[1][i] = default_ioport_writew;
- ioport_write_table[2][i] = default_ioport_writel;
+ ioport_write_table[0][i] = NULL;
+ ioport_write_table[1][i] = NULL;
+ ioport_write_table[2][i] = NULL;
ioport_opaque[i] = NULL;
}
}
+bool isa_is_ioport_assigned(pio_addr_t start)
+{
+ return (ioport_read_table[0][start] || ioport_write_table[0][start] ||
+ ioport_read_table[1][start] || ioport_write_table[1][start] ||
+ ioport_read_table[2][start] || ioport_write_table[2][start]);
+}
+
/***********************************************************/
-void cpu_outb(CPUState *env, int addr, int val)
+void cpu_outb(pio_addr_t addr, uint8_t val)
{
- LOG_IOPORT("outb: %04x %02x\n", addr, val);
+ LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
+ trace_cpu_out(addr, val);
ioport_write(0, addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
}
-void cpu_outw(CPUState *env, int addr, int val)
+void cpu_outw(pio_addr_t addr, uint16_t val)
{
- LOG_IOPORT("outw: %04x %04x\n", addr, val);
+ LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
+ trace_cpu_out(addr, val);
ioport_write(1, addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
}
-void cpu_outl(CPUState *env, int addr, int val)
+void cpu_outl(pio_addr_t addr, uint32_t val)
{
- LOG_IOPORT("outl: %04x %08x\n", addr, val);
+ LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
+ trace_cpu_out(addr, val);
ioport_write(2, addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
}
-int cpu_inb(CPUState *env, int addr)
+uint8_t cpu_inb(pio_addr_t addr)
{
- int val;
+ uint8_t val;
val = ioport_read(0, addr);
- LOG_IOPORT("inb : %04x %02x\n", addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
+ trace_cpu_in(addr, val);
+ LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
return val;
}
-int cpu_inw(CPUState *env, int addr)
+uint16_t cpu_inw(pio_addr_t addr)
{
- int val;
+ uint16_t val;
val = ioport_read(1, addr);
- LOG_IOPORT("inw : %04x %04x\n", addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
+ trace_cpu_in(addr, val);
+ LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
return val;
}
-int cpu_inl(CPUState *env, int addr)
+uint32_t cpu_inl(pio_addr_t addr)
{
- int val;
+ uint32_t val;
val = ioport_read(2, addr);
- LOG_IOPORT("inl : %04x %08x\n", addr, val);
-#ifdef CONFIG_KQEMU
- if (env)
- env->last_io_time = cpu_get_time_fast();
-#endif
+ trace_cpu_in(addr, val);
+ LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
return val;
}
-
projects / qemu.git / blobdiff