static bool addrrange_intersects(AddrRange r1, AddrRange r2)
{
- return (r1.start >= r2.start && r1.start < r2.start + r2.size)
- || (r2.start >= r1.start && r2.start < r1.start + r1.size);
+ return (r1.start >= r2.start && (r1.start - r2.start) < r2.size)
+ || (r2.start >= r1.start && (r2.start - r1.start) < r1.size);
}
static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
AddrRange addr;
uint8_t dirty_log_mask;
bool readable;
+ bool readonly;
};
/* Flattened global view of current active memory hierarchy. Kept in sorted
return a->mr == b->mr
&& addrrange_equal(a->addr, b->addr)
&& a->offset_in_region == b->offset_in_region
- && a->readable == b->readable;
+ && a->readable == b->readable
+ && a->readonly == b->readonly;
}
static void flatview_init(FlatView *view)
&& r1->mr == r2->mr
&& r1->offset_in_region + r1->addr.size == r2->offset_in_region
&& r1->dirty_log_mask == r2->dirty_log_mask
- && r1->readable == r2->readable;
+ && r1->readable == r2->readable
+ && r1->readonly == r2->readonly;
}
/* Attempt to simplify a view by merging ajacent ranges */
}
}
+static void memory_region_read_accessor(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t *value,
+ unsigned size,
+ unsigned shift,
+ uint64_t mask)
+{
+ MemoryRegion *mr = opaque;
+ uint64_t tmp;
+
+ tmp = mr->ops->read(mr->opaque, addr, size);
+ *value |= (tmp & mask) << shift;
+}
+
+static void memory_region_write_accessor(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t *value,
+ unsigned size,
+ unsigned shift,
+ uint64_t mask)
+{
+ MemoryRegion *mr = opaque;
+ uint64_t tmp;
+
+ tmp = (*value >> shift) & mask;
+ mr->ops->write(mr->opaque, addr, tmp, size);
+}
+
+static void access_with_adjusted_size(target_phys_addr_t addr,
+ uint64_t *value,
+ unsigned size,
+ unsigned access_size_min,
+ unsigned access_size_max,
+ void (*access)(void *opaque,
+ target_phys_addr_t addr,
+ uint64_t *value,
+ unsigned size,
+ unsigned shift,
+ uint64_t mask),
+ void *opaque)
+{
+ uint64_t access_mask;
+ unsigned access_size;
+ unsigned i;
+
+ if (!access_size_min) {
+ access_size_min = 1;
+ }
+ if (!access_size_max) {
+ access_size_max = 4;
+ }
+ access_size = MAX(MIN(size, access_size_max), access_size_min);
+ access_mask = -1ULL >> (64 - access_size * 8);
+ for (i = 0; i < size; i += access_size) {
+ /* FIXME: big-endian support */
+ access(opaque, addr + i, value, access_size, i * 8, access_mask);
+ }
+}
+
static void memory_region_prepare_ram_addr(MemoryRegion *mr);
static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
}
if (!fr->readable) {
- phys_offset &= TARGET_PAGE_MASK;
+ phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD;
+ }
+
+ if (fr->readonly) {
+ phys_offset |= IO_MEM_ROM;
}
cpu_register_physical_memory_log(fr->addr.start,
*data = ((uint64_t)1 << (width * 8)) - 1;
if (mrp) {
- *data = mrp->read(mr->opaque, offset - mrp->offset);
+ *data = mrp->read(mr->opaque, offset + mr->offset);
+ } else if (width == 2) {
+ mrp = find_portio(mr, offset, 1, false);
+ assert(mrp);
+ *data = mrp->read(mr->opaque, offset + mr->offset) |
+ (mrp->read(mr->opaque, offset + mr->offset + 1) << 8);
}
return;
}
- *data = mr->ops->read(mr->opaque, offset, width);
+ *data = 0;
+ access_with_adjusted_size(offset + mr->offset, data, width,
+ mr->ops->impl.min_access_size,
+ mr->ops->impl.max_access_size,
+ memory_region_read_accessor, mr);
}
static void memory_region_iorange_write(IORange *iorange,
const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true);
if (mrp) {
- mrp->write(mr->opaque, offset - mrp->offset, data);
+ mrp->write(mr->opaque, offset + mr->offset, data);
+ } else if (width == 2) {
+ mrp = find_portio(mr, offset, 1, false);
+ assert(mrp);
+ mrp->write(mr->opaque, offset + mr->offset, data & 0xff);
+ mrp->write(mr->opaque, offset + mr->offset + 1, data >> 8);
}
return;
}
- mr->ops->write(mr->opaque, offset, data, width);
+ access_with_adjusted_size(offset + mr->offset, &data, width,
+ mr->ops->impl.min_access_size,
+ mr->ops->impl.max_access_size,
+ memory_region_write_accessor, mr);
}
static const IORangeOps memory_region_iorange_ops = {
static void render_memory_region(FlatView *view,
MemoryRegion *mr,
target_phys_addr_t base,
- AddrRange clip)
+ AddrRange clip,
+ bool readonly)
{
MemoryRegion *subregion;
unsigned i;
AddrRange tmp;
base += mr->addr;
+ readonly |= mr->readonly;
tmp = addrrange_make(base, mr->size);
if (mr->alias) {
base -= mr->alias->addr;
base -= mr->alias_offset;
- render_memory_region(view, mr->alias, base, clip);
+ render_memory_region(view, mr->alias, base, clip, readonly);
return;
}
/* Render subregions in priority order. */
QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
- render_memory_region(view, subregion, base, clip);
+ render_memory_region(view, subregion, base, clip, readonly);
}
if (!mr->terminates) {
fr.addr = addrrange_make(base, now);
fr.dirty_log_mask = mr->dirty_log_mask;
fr.readable = mr->readable;
+ fr.readonly = readonly;
flatview_insert(view, i, &fr);
++i;
base += now;
fr.addr = addrrange_make(base, remain);
fr.dirty_log_mask = mr->dirty_log_mask;
fr.readable = mr->readable;
+ fr.readonly = readonly;
flatview_insert(view, i, &fr);
}
}
flatview_init(&view);
- render_memory_region(&view, mr, 0, addrrange_make(0, INT64_MAX));
+ render_memory_region(&view, mr, 0, addrrange_make(0, INT64_MAX), false);
flatview_simplify(&view);
return view;
mr->offset = 0;
mr->terminates = false;
mr->readable = true;
+ mr->readonly = false;
mr->destructor = memory_region_destructor_none;
mr->priority = 0;
mr->may_overlap = false;
unsigned size)
{
MemoryRegion *mr = _mr;
- unsigned access_size, access_size_min, access_size_max;
- uint64_t access_mask;
- uint32_t data = 0, tmp;
- unsigned i;
+ uint64_t data = 0;
if (!memory_region_access_valid(mr, addr, size)) {
return -1U; /* FIXME: better signalling */
}
/* FIXME: support unaligned access */
-
- access_size_min = mr->ops->impl.min_access_size;
- if (!access_size_min) {
- access_size_min = 1;
- }
- access_size_max = mr->ops->impl.max_access_size;
- if (!access_size_max) {
- access_size_max = 4;
- }
- access_size = MAX(MIN(size, access_size_max), access_size_min);
- access_mask = -1ULL >> (64 - access_size * 8);
- addr += mr->offset;
- for (i = 0; i < size; i += access_size) {
- /* FIXME: big-endian support */
- tmp = mr->ops->read(mr->opaque, addr + i, access_size);
- data |= (tmp & access_mask) << (i * 8);
- }
+ access_with_adjusted_size(addr + mr->offset, &data, size,
+ mr->ops->impl.min_access_size,
+ mr->ops->impl.max_access_size,
+ memory_region_read_accessor, mr);
return data;
}
uint64_t data)
{
MemoryRegion *mr = _mr;
- unsigned access_size, access_size_min, access_size_max;
- uint64_t access_mask;
- unsigned i;
if (!memory_region_access_valid(mr, addr, size)) {
return; /* FIXME: better signalling */
}
/* FIXME: support unaligned access */
-
- access_size_min = mr->ops->impl.min_access_size;
- if (!access_size_min) {
- access_size_min = 1;
- }
- access_size_max = mr->ops->impl.max_access_size;
- if (!access_size_max) {
- access_size_max = 4;
- }
- access_size = MAX(MIN(size, access_size_max), access_size_min);
- access_mask = -1ULL >> (64 - access_size * 8);
- addr += mr->offset;
- for (i = 0; i < size; i += access_size) {
- /* FIXME: big-endian support */
- mr->ops->write(mr->opaque, addr + i, (data >> (i * 8)) & access_mask,
- access_size);
- }
+ access_with_adjusted_size(addr + mr->offset, &data, size,
+ mr->ops->impl.min_access_size,
+ mr->ops->impl.max_access_size,
+ memory_region_write_accessor, mr);
}
static uint32_t memory_region_read_thunk_b(void *mr, target_phys_addr_t addr)
void memory_region_init_rom_device(MemoryRegion *mr,
const MemoryRegionOps *ops,
+ void *opaque,
DeviceState *dev,
const char *name,
uint64_t size)
{
memory_region_init(mr, name, size);
+ mr->ops = ops;
+ mr->opaque = opaque;
mr->terminates = true;
mr->destructor = memory_region_destructor_rom_device;
mr->ram_addr = qemu_ram_alloc(dev, name, size);
void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
{
- /* FIXME */
+ if (mr->readonly != readonly) {
+ mr->readonly = readonly;
+ memory_region_update_topology();
+ }
}
void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable)
assert(mr->terminates);
- return qemu_get_ram_ptr(mr->ram_addr);
+ return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
}
static void memory_region_update_coalesced_range(MemoryRegion *mr)
if (subregion->may_overlap || other->may_overlap) {
continue;
}
- if (offset >= other->offset + other->size
- || offset + subregion->size <= other->offset) {
+ if (offset >= other->addr + other->size
+ || offset + subregion->size <= other->addr) {
continue;
}
- printf("warning: subregion collision %llx/%llx vs %llx/%llx\n",
+#if 0
+ printf("warning: subregion collision %llx/%llx (%s) "
+ "vs %llx/%llx (%s)\n",
(unsigned long long)offset,
(unsigned long long)subregion->size,
- (unsigned long long)other->offset,
- (unsigned long long)other->size);
+ subregion->name,
+ (unsigned long long)other->addr,
+ (unsigned long long)other->size,
+ other->name);
+#endif
}
QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
if (subregion->priority >= other->priority) {
address_space_io.root = mr;
memory_region_update_topology();
}
+
+typedef struct MemoryRegionList MemoryRegionList;
+
+struct MemoryRegionList {
+ const MemoryRegion *mr;
+ bool printed;
+ QTAILQ_ENTRY(MemoryRegionList) queue;
+};
+
+typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
+
+static void mtree_print_mr(fprintf_function mon_printf, void *f,
+ const MemoryRegion *mr, unsigned int level,
+ target_phys_addr_t base,
+ MemoryRegionListHead *alias_print_queue)
+{
+ MemoryRegionList *new_ml, *ml, *next_ml;
+ MemoryRegionListHead submr_print_queue;
+ const MemoryRegion *submr;
+ unsigned int i;
+
+ if (!mr) {
+ return;
+ }
+
+ for (i = 0; i < level; i++) {
+ mon_printf(f, " ");
+ }
+
+ if (mr->alias) {
+ MemoryRegionList *ml;
+ bool found = false;
+
+ /* check if the alias is already in the queue */
+ QTAILQ_FOREACH(ml, alias_print_queue, queue) {
+ if (ml->mr == mr->alias && !ml->printed) {
+ found = true;
+ }
+ }
+
+ if (!found) {
+ ml = g_new(MemoryRegionList, 1);
+ ml->mr = mr->alias;
+ ml->printed = false;
+ QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
+ }
+ mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): alias %s @%s "
+ TARGET_FMT_plx "-" TARGET_FMT_plx "\n",
+ base + mr->addr,
+ base + mr->addr + (target_phys_addr_t)mr->size - 1,
+ mr->priority,
+ mr->name,
+ mr->alias->name,
+ mr->alias_offset,
+ mr->alias_offset + (target_phys_addr_t)mr->size - 1);
+ } else {
+ mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n",
+ base + mr->addr,
+ base + mr->addr + (target_phys_addr_t)mr->size - 1,
+ mr->priority,
+ mr->name);
+ }
+
+ QTAILQ_INIT(&submr_print_queue);
+
+ QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
+ new_ml = g_new(MemoryRegionList, 1);
+ new_ml->mr = submr;
+ QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
+ if (new_ml->mr->addr < ml->mr->addr ||
+ (new_ml->mr->addr == ml->mr->addr &&
+ new_ml->mr->priority > ml->mr->priority)) {
+ QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
+ new_ml = NULL;
+ break;
+ }
+ }
+ if (new_ml) {
+ QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
+ }
+ }
+
+ QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
+ mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
+ alias_print_queue);
+ }
+
+ QTAILQ_FOREACH_SAFE(next_ml, &submr_print_queue, queue, ml) {
+ g_free(ml);
+ }
+}
+
+void mtree_info(fprintf_function mon_printf, void *f)
+{
+ MemoryRegionListHead ml_head;
+ MemoryRegionList *ml, *ml2;
+
+ QTAILQ_INIT(&ml_head);
+
+ mon_printf(f, "memory\n");
+ mtree_print_mr(mon_printf, f, address_space_memory.root, 0, 0, &ml_head);
+
+ /* print aliased regions */
+ QTAILQ_FOREACH(ml, &ml_head, queue) {
+ if (!ml->printed) {
+ mon_printf(f, "%s\n", ml->mr->name);
+ mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
+ }
+ }
+
+ QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
+ g_free(ml2);
+ }
+
+ if (address_space_io.root &&
+ !QTAILQ_EMPTY(&address_space_io.root->subregions)) {
+ QTAILQ_INIT(&ml_head);
+ mon_printf(f, "I/O\n");
+ mtree_print_mr(mon_printf, f, address_space_io.root, 0, 0, &ml_head);
+ }
+}
projects / qemu.git / blobdiff