*
*/
-#include "qtest.h"
-#include "qemu-char.h"
-#include "ioport.h"
-#include "memory.h"
+#include "sysemu/qtest.h"
+#include "hw/qdev.h"
+#include "sysemu/char.h"
+#include "exec/ioport.h"
+#include "exec/memory.h"
#include "hw/irq.h"
-#include "sysemu.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/cpus.h"
#define MAX_IRQ 256
const char *qtest_chrdev;
const char *qtest_log;
-int qtest_allowed = 0;
+bool qtest_allowed;
+static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharDriverState *qtest_chr;
static GString *inbuf;
static int irq_levels[MAX_IRQ];
-static struct timeval start_time;
+static qemu_timeval start_time;
static bool qtest_opened;
-#define FMT_timeval "%" PRId64 ".%06" PRId64
+#define FMT_timeval "%ld.%06ld"
/**
* QTest Protocol
*
* Valid requests
*
+ * Clock management:
+ *
+ * The qtest client is completely in charge of the vm_clock. qtest commands
+ * let you adjust the value of the clock (monotonically). All the commands
+ * return the current value of the clock in nanoseconds.
+ *
+ * > clock_step
+ * < OK VALUE
+ *
+ * Advance the clock to the next deadline. Useful when waiting for
+ * asynchronous events.
+ *
+ * > clock_step NS
+ * < OK VALUE
+ *
+ * Advance the clock by NS nanoseconds.
+ *
+ * > clock_set NS
+ * < OK VALUE
+ *
+ * Advance the clock to NS nanoseconds (do nothing if it's already past).
+ *
+ * PIO and memory access:
+ *
* > outb ADDR VALUE
* < OK
*
* > inl ADDR
* < OK VALUE
*
+ * > writeb ADDR VALUE
+ * < OK
+ *
+ * > writew ADDR VALUE
+ * < OK
+ *
+ * > writel ADDR VALUE
+ * < OK
+ *
+ * > writeq ADDR VALUE
+ * < OK
+ *
+ * > readb ADDR
+ * < OK VALUE
+ *
+ * > readw ADDR
+ * < OK VALUE
+ *
+ * > readl ADDR
+ * < OK VALUE
+ *
+ * > readq ADDR
+ * < OK VALUE
+ *
* > read ADDR SIZE
* < OK DATA
*
* > write ADDR SIZE DATA
* < OK
*
- * Valid async messages:
- *
- * IRQ raise NUM
- * IRQ lower NUM
- *
* ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
*
* DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
* than the expected size, the value will be zero filled at the end of the data
* sequence.
*
- * NUM is an IRQ number.
+ * IRQ management:
+ *
+ * > irq_intercept_in QOM-PATH
+ * < OK
+ *
+ * > irq_intercept_out QOM-PATH
+ * < OK
+ *
+ * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
+ * QOM-PATH. When the pin is triggered, one of the following async messages
+ * will be printed to the qtest stream:
+ *
+ * IRQ raise NUM
+ * IRQ lower NUM
+ *
+ * where NUM is an IRQ number. For the PC, interrupts can be intercepted
+ * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
+ * NUM=0 even though it is remapped to GSI 2).
*/
static int hex2nib(char ch)
}
}
-static void qtest_get_time(struct timeval *tv)
+static void qtest_get_time(qemu_timeval *tv)
{
- gettimeofday(tv, NULL);
+ qemu_gettimeofday(tv);
tv->tv_sec -= start_time.tv_sec;
tv->tv_usec -= start_time.tv_usec;
if (tv->tv_usec < 0) {
static void qtest_send_prefix(CharDriverState *chr)
{
- struct timeval tv;
+ qemu_timeval tv;
if (!qtest_log_fp || !qtest_opened) {
return;
qtest_get_time(&tv);
fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
- tv.tv_sec, tv.tv_usec);
+ tv.tv_sec, (long) tv.tv_usec);
}
-static void qtest_send(CharDriverState *chr, const char *fmt, ...)
+static void GCC_FMT_ATTR(2, 3) qtest_send(CharDriverState *chr,
+ const char *fmt, ...)
{
va_list ap;
char buffer[1024];
len = vsnprintf(buffer, sizeof(buffer), fmt, ap);
va_end(ap);
- qemu_chr_fe_write(chr, (uint8_t *)buffer, len);
+ qemu_chr_fe_write_all(chr, (uint8_t *)buffer, len);
if (qtest_log_fp && qtest_opened) {
fprintf(qtest_log_fp, "%s", buffer);
}
}
+static void qtest_irq_handler(void *opaque, int n, int level)
+{
+ qemu_irq *old_irqs = opaque;
+ qemu_set_irq(old_irqs[n], level);
+
+ if (irq_levels[n] != level) {
+ CharDriverState *chr = qtest_chr;
+ irq_levels[n] = level;
+ qtest_send_prefix(chr);
+ qtest_send(chr, "IRQ %s %d\n",
+ level ? "raise" : "lower", n);
+ }
+}
+
static void qtest_process_command(CharDriverState *chr, gchar **words)
{
const gchar *command;
command = words[0];
if (qtest_log_fp) {
- struct timeval tv;
+ qemu_timeval tv;
int i;
qtest_get_time(&tv);
fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
- tv.tv_sec, tv.tv_usec);
+ tv.tv_sec, (long) tv.tv_usec);
for (i = 0; words[i]; i++) {
fprintf(qtest_log_fp, " %s", words[i]);
}
}
g_assert(command);
- if (strcmp(words[0], "outb") == 0 ||
- strcmp(words[0], "outw") == 0 ||
- strcmp(words[0], "outl") == 0) {
+ if (strcmp(words[0], "irq_intercept_out") == 0
+ || strcmp(words[0], "irq_intercept_in") == 0) {
+ DeviceState *dev;
+
+ g_assert(words[1]);
+ dev = DEVICE(object_resolve_path(words[1], NULL));
+ if (!dev) {
+ qtest_send_prefix(chr);
+ qtest_send(chr, "FAIL Unknown device\n");
+ return;
+ }
+
+ if (irq_intercept_dev) {
+ qtest_send_prefix(chr);
+ if (irq_intercept_dev != dev) {
+ qtest_send(chr, "FAIL IRQ intercept already enabled\n");
+ } else {
+ qtest_send(chr, "OK\n");
+ }
+ return;
+ }
+
+ if (words[0][14] == 'o') {
+ qemu_irq_intercept_out(&dev->gpio_out, qtest_irq_handler, dev->num_gpio_out);
+ } else {
+ qemu_irq_intercept_in(dev->gpio_in, qtest_irq_handler, dev->num_gpio_in);
+ }
+ irq_intercept_dev = dev;
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK\n");
+
+ } else if (strcmp(words[0], "outb") == 0 ||
+ strcmp(words[0], "outw") == 0 ||
+ strcmp(words[0], "outl") == 0) {
uint16_t addr;
uint32_t value;
g_assert(words[1] && words[2]);
- addr = strtol(words[1], NULL, 0);
- value = strtol(words[2], NULL, 0);
+ addr = strtoul(words[1], NULL, 0);
+ value = strtoul(words[2], NULL, 0);
if (words[0][3] == 'b') {
cpu_outb(addr, value);
uint32_t value = -1U;
g_assert(words[1]);
- addr = strtol(words[1], NULL, 0);
+ addr = strtoul(words[1], NULL, 0);
if (words[0][2] == 'b') {
value = cpu_inb(addr);
}
qtest_send_prefix(chr);
qtest_send(chr, "OK 0x%04x\n", value);
+ } else if (strcmp(words[0], "writeb") == 0 ||
+ strcmp(words[0], "writew") == 0 ||
+ strcmp(words[0], "writel") == 0 ||
+ strcmp(words[0], "writeq") == 0) {
+ uint64_t addr;
+ uint64_t value;
+
+ g_assert(words[1] && words[2]);
+ addr = strtoull(words[1], NULL, 0);
+ value = strtoull(words[2], NULL, 0);
+
+ if (words[0][5] == 'b') {
+ uint8_t data = value;
+ cpu_physical_memory_write(addr, &data, 1);
+ } else if (words[0][5] == 'w') {
+ uint16_t data = value;
+ tswap16s(&data);
+ cpu_physical_memory_write(addr, &data, 2);
+ } else if (words[0][5] == 'l') {
+ uint32_t data = value;
+ tswap32s(&data);
+ cpu_physical_memory_write(addr, &data, 4);
+ } else if (words[0][5] == 'q') {
+ uint64_t data = value;
+ tswap64s(&data);
+ cpu_physical_memory_write(addr, &data, 8);
+ }
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK\n");
+ } else if (strcmp(words[0], "readb") == 0 ||
+ strcmp(words[0], "readw") == 0 ||
+ strcmp(words[0], "readl") == 0 ||
+ strcmp(words[0], "readq") == 0) {
+ uint64_t addr;
+ uint64_t value = UINT64_C(-1);
+
+ g_assert(words[1]);
+ addr = strtoull(words[1], NULL, 0);
+
+ if (words[0][4] == 'b') {
+ uint8_t data;
+ cpu_physical_memory_read(addr, &data, 1);
+ value = data;
+ } else if (words[0][4] == 'w') {
+ uint16_t data;
+ cpu_physical_memory_read(addr, &data, 2);
+ value = tswap16(data);
+ } else if (words[0][4] == 'l') {
+ uint32_t data;
+ cpu_physical_memory_read(addr, &data, 4);
+ value = tswap32(data);
+ } else if (words[0][4] == 'q') {
+ cpu_physical_memory_read(addr, &value, 8);
+ tswap64s(&value);
+ }
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK 0x%016" PRIx64 "\n", value);
} else if (strcmp(words[0], "read") == 0) {
uint64_t addr, len, i;
uint8_t *data;
g_assert(words[1] && words[2]);
- addr = strtoul(words[1], NULL, 0);
- len = strtoul(words[2], NULL, 0);
+ addr = strtoull(words[1], NULL, 0);
+ len = strtoull(words[2], NULL, 0);
data = g_malloc(len);
cpu_physical_memory_read(addr, data, len);
size_t data_len;
g_assert(words[1] && words[2] && words[3]);
- addr = strtoul(words[1], NULL, 0);
- len = strtoul(words[2], NULL, 0);
+ addr = strtoull(words[1], NULL, 0);
+ len = strtoull(words[2], NULL, 0);
data_len = strlen(words[3]);
if (data_len < 3) {
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+ } else if (strcmp(words[0], "clock_step") == 0) {
+ int64_t ns;
+
+ if (words[1]) {
+ ns = strtoll(words[1], NULL, 0);
+ } else {
+ ns = qemu_clock_deadline(vm_clock);
+ }
+ qtest_clock_warp(qemu_get_clock_ns(vm_clock) + ns);
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_get_clock_ns(vm_clock));
+ } else if (strcmp(words[0], "clock_set") == 0) {
+ int64_t ns;
+
+ g_assert(words[1]);
+ ns = strtoll(words[1], NULL, 0);
+ qtest_clock_warp(ns);
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_get_clock_ns(vm_clock));
} else {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown command `%s'\n", words[0]);
for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
irq_levels[i] = 0;
}
- gettimeofday(&start_time, NULL);
+ qemu_gettimeofday(&start_time);
qtest_opened = true;
if (qtest_log_fp) {
fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
- start_time.tv_sec, start_time.tv_usec);
+ start_time.tv_sec, (long) start_time.tv_usec);
}
break;
case CHR_EVENT_CLOSED:
qtest_opened = false;
if (qtest_log_fp) {
- struct timeval tv;
+ qemu_timeval tv;
qtest_get_time(&tv);
fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
- tv.tv_sec, tv.tv_usec);
+ tv.tv_sec, (long) tv.tv_usec);
}
break;
default:
}
}
-static void qtest_set_irq(void *opaque, int irq, int level)
-{
- CharDriverState *chr = qtest_chr;
- bool changed;
-
- changed = (irq_levels[irq] != level);
- irq_levels[irq] = level;
-
- if (changed) {
- qtest_send_prefix(chr);
- qtest_send(chr, "IRQ %s %d\n",
- level ? "raise" : "lower", irq);
- }
-}
-
int qtest_init(void)
{
CharDriverState *chr;
g_assert(qtest_chrdev != NULL);
+ configure_icount("0");
chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
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