virtio: add virtio_bus_get_dev_path.

[qemu.git] / target-alpha / helper.c

diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index d0e4db26c282dcbd697f8a2af7459b3209df855f..5741ec25ea8f0f384ec04e2365287603236ad93b 100644 (file)
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -22,10 +22,10 @@
 #include <stdio.h>
 
 #include "cpu.h"
-#include "exec-all.h"
-#include "softfloat.h"
+#include "fpu/softfloat.h"
+#include "helper.h"
 
-uint64_t cpu_alpha_load_fpcr (CPUState *env)
+uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env)
 {
     uint64_t r = 0;
     uint8_t t;
@@ -82,7 +82,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env)
         break;
     }
 
-    if (env->fpcr_dnz) {
+    if (env->fp_status.flush_inputs_to_zero) {
         r |= FPCR_DNZ;
     }
     if (env->fpcr_dnod) {
@@ -95,7 +95,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env)
     return r;
 }
 
-void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
+void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
 {
     uint8_t t;
 
@@ -151,24 +151,32 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
     }
     env->fpcr_dyn_round = t;
 
-    env->fpcr_flush_to_zero
-      = (val & (FPCR_UNDZ|FPCR_UNFD)) == (FPCR_UNDZ|FPCR_UNFD);
-
-    env->fpcr_dnz = (val & FPCR_DNZ) != 0;
     env->fpcr_dnod = (val & FPCR_DNOD) != 0;
     env->fpcr_undz = (val & FPCR_UNDZ) != 0;
+    env->fpcr_flush_to_zero = env->fpcr_dnod & env->fpcr_undz;
+    env->fp_status.flush_inputs_to_zero = (val & FPCR_DNZ) != 0;
+}
+
+uint64_t helper_load_fpcr(CPUAlphaState *env)
+{
+    return cpu_alpha_load_fpcr(env);
+}
+
+void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
+{
+    cpu_alpha_store_fpcr(env, val);
 }
 
 #if defined(CONFIG_USER_ONLY)
-int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
-                                int mmu_idx, int is_softmmu)
+int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address,
+                               int rw, int mmu_idx)
 {
     env->exception_index = EXCP_MMFAULT;
     env->trap_arg0 = address;
     return 1;
 }
 #else
-void swap_shadow_regs(CPUState *env)
+void swap_shadow_regs(CPUAlphaState *env)
 {
     uint64_t i0, i1, i2, i3, i4, i5, i6, i7;
 
@@ -201,7 +209,7 @@ void swap_shadow_regs(CPUState *env)
 }
 
 /* Returns the OSF/1 entMM failure indication, or -1 on success.  */
-static int get_physical_address(CPUState *env, target_ulong addr,
+static int get_physical_address(CPUAlphaState *env, target_ulong addr,
                                 int prot_need, int mmu_idx,
                                 target_ulong *pphys, int *pprot)
 {
@@ -220,14 +228,18 @@ static int get_physical_address(CPUState *env, target_ulong addr,
 
     /* Translate the superpage.  */
     /* ??? When we do more than emulate Unix PALcode, we'll need to
-       determine which superpage is actually active.  */
-    if (saddr < 0 && (saddr >> (TARGET_VIRT_ADDR_SPACE_BITS - 2) & 3) == 2) {
-        /* User-space cannot access kseg addresses.  */
+       determine which KSEG is actually active.  */
+    if (saddr < 0 && ((saddr >> 41) & 3) == 2) {
+        /* User-space cannot access KSEG addresses.  */
         if (mmu_idx != MMU_KERNEL_IDX) {
             goto exit;
         }
 
+        /* For the benefit of the Typhoon chipset, move bit 40 to bit 43.
+           We would not do this if the 48-bit KSEG is enabled.  */
         phys = saddr & ((1ull << 40) - 1);
+        phys |= (saddr & (1ull << 40)) << 3;
+
         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         ret = -1;
         goto exit;
@@ -303,7 +315,7 @@ static int get_physical_address(CPUState *env, target_ulong addr,
     return ret;
 }
 
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr)
 {
     target_ulong phys;
     int prot, fail;
@@ -312,8 +324,8 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
     return (fail >= 0 ? -1 : phys);
 }
 
-int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
-                               int mmu_idx, int is_softmmu)
+int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw,
+                               int mmu_idx)
 {
     target_ulong phys;
     int prot, fail;
@@ -333,8 +345,10 @@ int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
 }
 #endif /* USER_ONLY */
 
-void do_interrupt (CPUState *env)
+void alpha_cpu_do_interrupt(CPUState *cs)
 {
+    AlphaCPU *cpu = ALPHA_CPU(cs);
+    CPUAlphaState *env = &cpu->env;
     int i = env->exception_index;
 
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -450,7 +464,7 @@ void do_interrupt (CPUState *env)
 #endif /* !USER_ONLY */
 }
 
-void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
+void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_fprintf,
                      int flags)
 {
     static const char *linux_reg_names[] = {
@@ -481,3 +495,32 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
     }
     cpu_fprintf(f, "\n");
 }
+
+/* This should only be called from translate, via gen_excp.
+   We expect that ENV->PC has already been updated.  */
+void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
+{
+    env->exception_index = excp;
+    env->error_code = error;
+    cpu_loop_exit(env);
+}
+
+/* This may be called from any of the helpers to set up EXCEPTION_INDEX.  */
+void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
+                                int excp, int error)
+{
+    env->exception_index = excp;
+    env->error_code = error;
+    if (retaddr) {
+        cpu_restore_state(env, retaddr);
+    }
+    cpu_loop_exit(env);
+}
+
+void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
+                              int exc, uint64_t mask)
+{
+    env->trap_arg0 = exc;
+    env->trap_arg1 = mask;
+    dynamic_excp(env, retaddr, EXCP_ARITH, 0);
+}