*/
#include "cpu.h"
-#include "disas.h"
-#include "host-utils.h"
+#include "disas/disas.h"
+#include "qemu/host-utils.h"
#include "tcg-op.h"
#include "helper.h"
/* register names */
static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
-#include "gen-icount.h"
+#include "exec/gen-icount.h"
-static void alpha_translate_init(void)
+void alpha_translate_init(void)
{
int i;
char *p;
}
#if defined(CONFIG_SOFTFLOAT_INLINE)
- /* ??? The "softfloat.h" interface is to call set_float_rounding_mode.
+ /* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_mode.
With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
sets the one field. */
tcg_gen_st8_i32(tmp, cpu_env,
tcg_temp_free(tmp1); \
} \
}
-ARITH3(umulh)
ARITH3(cmpbge)
ARITH3(minub8)
ARITH3(minsb8)
case 0x3C:
/* WHAMI */
tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
- offsetof(CPUAlphaState, cpu_index));
+ -offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
break;
default:
case 253:
/* WAIT */
tmp = tcg_const_i64(1);
- tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted));
+ tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) +
+ offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HLT, 0);
case 252:
break;
case 0x30:
/* UMULH */
- gen_umulh(ra, rb, rc, islit, lit);
+ {
+ TCGv low;
+ if (unlikely(rc == 31)){
+ break;
+ }
+ if (ra == 31) {
+ tcg_gen_movi_i64(cpu_ir[rc], 0);
+ break;
+ }
+ low = tcg_temp_new();
+ if (islit) {
+ tcg_gen_movi_tl(low, lit);
+ tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], low);
+ } else {
+ tcg_gen_mulu2_i64(low, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
+ }
+ tcg_temp_free(low);
+ }
break;
case 0x40:
/* MULL/V */
int max_insns;
pc_start = tb->pc;
- gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
ctx.tb = tb;
ctx.env = env;
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_icount_start();
+ gen_tb_start();
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
}
}
if (search_pc) {
- j = gen_opc_ptr - gen_opc_buf;
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
if (lj < j) {
lj++;
while (lj < j)
- gen_opc_instr_start[lj++] = 0;
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
}
- gen_opc_pc[lj] = ctx.pc;
- gen_opc_instr_start[lj] = 1;
- gen_opc_icount[lj] = num_insns;
+ tcg_ctx.gen_opc_pc[lj] = ctx.pc;
+ tcg_ctx.gen_opc_instr_start[lj] = 1;
+ tcg_ctx.gen_opc_icount[lj] = num_insns;
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
insn = cpu_ldl_code(env, ctx.pc);
num_insns++;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.pc);
}
or exhaust instruction count, stop generation. */
if (ret == NO_EXIT
&& ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0
- || gen_opc_ptr >= gen_opc_end
+ || tcg_ctx.gen_opc_ptr >= gen_opc_end
|| num_insns >= max_insns
|| singlestep
|| env->singlestep_enabled)) {
abort();
}
- gen_icount_end(tb, num_insns);
- *gen_opc_ptr = INDEX_op_end;
+ gen_tb_end(tb, num_insns);
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
if (search_pc) {
- j = gen_opc_ptr - gen_opc_buf;
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
lj++;
while (lj <= j)
- gen_opc_instr_start[lj++] = 0;
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
} else {
tb->size = ctx.pc - pc_start;
tb->icount = num_insns;
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(pc_start, ctx.pc - pc_start, 1);
+ log_target_disas(env, pc_start, ctx.pc - pc_start, 1);
qemu_log("\n");
}
#endif
gen_intermediate_code_internal(env, tb, 1);
}
-struct cpu_def_t {
- const char *name;
- int implver, amask;
-};
-
-static const struct cpu_def_t cpu_defs[] = {
- { "ev4", IMPLVER_2106x, 0 },
- { "ev5", IMPLVER_21164, 0 },
- { "ev56", IMPLVER_21164, AMASK_BWX },
- { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "21064", IMPLVER_2106x, 0 },
- { "21164", IMPLVER_21164, 0 },
- { "21164a", IMPLVER_21164, AMASK_BWX },
- { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
-};
-
-CPUAlphaState * cpu_alpha_init (const char *cpu_model)
-{
- AlphaCPU *cpu;
- CPUAlphaState *env;
- int implver, amask, i, max;
-
- cpu = ALPHA_CPU(object_new(TYPE_ALPHA_CPU));
- env = &cpu->env;
-
- alpha_translate_init();
-
- /* Default to ev67; no reason not to emulate insns by default. */
- implver = IMPLVER_21264;
- amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI
- | AMASK_TRAP | AMASK_PREFETCH);
-
- max = ARRAY_SIZE(cpu_defs);
- for (i = 0; i < max; i++) {
- if (strcmp (cpu_model, cpu_defs[i].name) == 0) {
- implver = cpu_defs[i].implver;
- amask = cpu_defs[i].amask;
- break;
- }
- }
- env->implver = implver;
- env->amask = amask;
-
- qemu_init_vcpu(env);
- return env;
-}
-
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos)
{
- env->pc = gen_opc_pc[pc_pos];
+ env->pc = tcg_ctx.gen_opc_pc[pc_pos];
}
projects / qemu.git / blobdiff