target-ppc: fix flags computation for tcg_gen_qemu_st

[qemu.git] / target-alpha / translate.c

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index ebfe4260db136b03835fe758c5a02595546bab60..5c88a12a999776b520b08311b98e11ac289b4cdb 100644 (file)
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -940,12 +940,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
                 if (ra != 31) {
                     if (islit)
                         tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
-                    else {
-                        TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
-                        tcg_gen_not_i64(tmp, cpu_ir[rb]);
-                        tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
-                        tcg_temp_free(tmp);
-                    }
+                    else
+                        tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
                 } else
                     tcg_gen_movi_i64(cpu_ir[rc], 0);
             }
@@ -988,12 +984,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
                 if (ra != 31) {
                     if (islit)
                         tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
-                    else {
-                        TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
-                        tcg_gen_not_i64(tmp, cpu_ir[rb]);
-                        tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
-                        tcg_temp_free(tmp);
-                    }
+                    else
+                        tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
                 } else {
                     if (islit)
                         tcg_gen_movi_i64(cpu_ir[rc], ~lit);
@@ -1032,12 +1024,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
                 if (ra != 31) {
                     if (islit)
                         tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
-                    else {
-                        TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
-                        tcg_gen_not_i64(tmp, cpu_ir[rb]);
-                        tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
-                        tcg_temp_free(tmp);
-                    }
+                    else
+                        tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
                 } else {
                     if (islit)
                         tcg_gen_movi_i64(cpu_ir[rc], ~lit);
@@ -1646,12 +1634,12 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
         break;
 #endif
     case 0x1A:
-        if (ra != 31)
-            tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
         if (rb != 31)
             tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
         else
             tcg_gen_movi_i64(cpu_pc, 0);
+        if (ra != 31)
+            tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
         /* Those four jumps only differ by the branch prediction hint */
         switch (fn2) {
         case 0x0: