#ifndef QEMU_ARM_CPU_QOM_H
#define QEMU_ARM_CPU_QOM_H
-#include "qemu/cpu.h"
-#include "cpu.h"
+#include "qom/cpu.h"
#define TYPE_ARM_CPU "arm-cpu"
/**
* ARMCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An ARM CPU model.
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} ARMCPUClass;
CPUARMState env;
+ /* Coprocessor information */
+ GHashTable *cp_regs;
+ /* For marshalling (mostly coprocessor) register state between the
+ * kernel and QEMU (for KVM) and between two QEMUs (for migration),
+ * we use these arrays.
+ */
+ /* List of register indexes managed via these arrays; (full KVM style
+ * 64 bit indexes, not CPRegInfo 32 bit indexes)
+ */
+ uint64_t *cpreg_indexes;
+ /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
+ uint64_t *cpreg_values;
+ /* When using KVM, keeps a copy of the initial state of the VCPU,
+ * so that on reset we can feed the reset values back into the kernel.
+ */
+ uint64_t *cpreg_reset_values;
+ /* Length of the indexes, values, reset_values arrays */
+ int32_t cpreg_array_len;
+ /* These are used only for migration: incoming data arrives in
+ * these fields and is sanity checked in post_load before copying
+ * to the working data structures above.
+ */
+ uint64_t *cpreg_vmstate_indexes;
+ uint64_t *cpreg_vmstate_values;
+ int32_t cpreg_vmstate_array_len;
+
/* The instance init functions for implementation-specific subclasses
* set these fields to specify the implementation-dependent values of
* various constant registers and reset values of non-constant
* prefix means a constant register.
*/
uint32_t midr;
+ uint32_t reset_fpsid;
+ uint32_t mvfr0;
+ uint32_t mvfr1;
+ uint32_t ctr;
+ uint32_t reset_sctlr;
+ uint32_t id_pfr0;
+ uint32_t id_pfr1;
+ uint32_t id_dfr0;
+ uint32_t id_afr0;
+ uint32_t id_mmfr0;
+ uint32_t id_mmfr1;
+ uint32_t id_mmfr2;
+ uint32_t id_mmfr3;
+ uint32_t id_isar0;
+ uint32_t id_isar1;
+ uint32_t id_isar2;
+ uint32_t id_isar3;
+ uint32_t id_isar4;
+ uint32_t id_isar5;
+ uint32_t clidr;
+ /* The elements of this array are the CCSIDR values for each cache,
+ * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+ */
+ uint32_t ccsidr[16];
+ uint32_t reset_cbar;
+ uint32_t reset_auxcr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
{
- return ARM_CPU(container_of(env, ARMCPU, env));
+ return container_of(env, ARMCPU, env);
}
#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
-void arm_cpu_realize(ARMCPU *cpu);
+#define ENV_OFFSET offsetof(ARMCPU, env)
+
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_arm_cpu;
+#endif
+
+void register_cp_regs_for_features(ARMCPU *cpu);
+void init_cpreg_list(ARMCPU *cpu);
+
+void arm_cpu_do_interrupt(CPUState *cpu);
+void arm_v7m_cpu_do_interrupt(CPUState *cpu);
+
+void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+
+hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif