target-cris: Introduce QOM realizefn for CRISCPU

[qemu.git] / target-cris / cpu.h

diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 754953cda053c3fa990d4478bb641843eacc8f30..257cb52be25f4644acc608e73deb4a2945506416 100644 (file)
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -15,15 +15,19 @@
  * General Public License for more details.
  *
  * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef CPU_CRIS_H
 #define CPU_CRIS_H
 
+#include "config.h"
+#include "qemu-common.h"
+
 #define TARGET_LONG_BITS 32
 
-#include "cpu-defs.h"
+#define CPUArchState struct CPUCRISState
+
+#include "exec/cpu-defs.h"
 
 #define TARGET_HAS_ICE 1
 
@@ -35,6 +39,9 @@
 #define EXCP_IRQ        4
 #define EXCP_BREAK      5
 
+/* CRIS-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_FP  8
 #define R_SP  14
@@ -48,6 +55,7 @@
 #define PR_WZ  4
 #define PR_EXS 5
 #define PR_EDA 6
+#define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
 #define PR_MOF 7
 #define PR_DZ  8
 #define PR_EBP 9
@@ -56,16 +64,19 @@
 #define PR_NRP 12
 #define PR_CCS 13
 #define PR_USP 14
+#define PRV10_BRP 14
 #define PR_SPC 15
 
 /* CPU flags.  */
 #define Q_FLAG 0x80000000
-#define M_FLAG 0x40000000
+#define M_FLAG_V32 0x40000000
+#define PFIX_FLAG 0x800      /* CRISv10 Only.  */
+#define F_FLAG_V10 0x400
+#define P_FLAG_V10 0x200
 #define S_FLAG 0x200
 #define R_FLAG 0x100
 #define P_FLAG 0x80
-#define U_FLAG 0x40
-#define P_FLAG 0x80
+#define M_FLAG_V10 0x80
 #define U_FLAG 0x40
 #define I_FLAG 0x20
 #define X_FLAG 0x10
@@ -93,9 +104,6 @@
 #define CC_A   14
 #define CC_P   15
 
-/* Internal flags for the implementation.  */
-#define F_DELAYSLOT 1
-
 #define NB_MMU_MODES 2
 
 typedef struct CPUCRISState {
@@ -103,7 +111,7 @@ typedef struct CPUCRISState {
        /* P0 - P15 are referred to as special registers in the docs.  */
        uint32_t pregs[16];
 
-       /* Pseudo register for the PC. Not directly accessable on CRIS.  */
+       /* Pseudo register for the PC. Not directly accessible on CRIS.  */
        uint32_t pc;
 
        /* Pseudo register for the kernel stack.  */
@@ -125,6 +133,8 @@ typedef struct CPUCRISState {
        /* X flag at the time of cc snapshot.  */
        int cc_x;
 
+       /* CRIS has certain insns that lockout interrupts.  */
+       int locked_irq;
        int interrupt_vector;
        int fault_vector;
        int trap_vector;
@@ -156,11 +166,15 @@ typedef struct CPUCRISState {
        } tlbsets[2][4][16];
 
        CPU_COMMON
+
+       /* Members after CPU_COMMON are preserved across resets.  */
+       void *load_info;
 } CPUCRISState;
 
-CPUCRISState *cpu_cris_init(const char *cpu_model);
+#include "cpu-qom.h"
+
+CRISCPU *cpu_cris_init(const char *cpu_model);
 int cpu_cris_exec(CPUCRISState *s);
-void cpu_cris_close(CPUCRISState *s);
 void do_interrupt(CPUCRISState *env);
 /* you can call this signal handler from your SIGBUS and SIGSEGV
    signal handlers to inform the virtual CPU of exceptions. non zero
@@ -184,6 +198,7 @@ enum {
     CC_OP_MULS,
     CC_OP_MULU,
     CC_OP_DSTEP,
+    CC_OP_MSTEP,
     CC_OP_BOUND,
 
     CC_OP_OR,
@@ -199,8 +214,18 @@ enum {
 #define TARGET_PAGE_BITS 13
 #define MMAP_SHIFT TARGET_PAGE_BITS
 
-#define CPUState CPUCRISState
-#define cpu_init cpu_cris_init
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+
+static inline CPUCRISState *cpu_init(const char *cpu_model)
+{
+    CRISCPU *cpu = cpu_cris_init(cpu_model);
+    if (cpu == NULL) {
+        return NULL;
+    }
+    return &cpu->env;
+}
+
 #define cpu_exec cpu_cris_exec
 #define cpu_gen_code cpu_cris_gen_code
 #define cpu_signal_handler cpu_cris_signal_handler
@@ -211,16 +236,17 @@ enum {
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user
 #define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUCRISState *env)
 {
        return !!(env->pregs[PR_CCS] & U_FLAG);
 }
 
-int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
-                              int mmu_idx, int is_softmmu);
+int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+                              int mmu_idx);
+#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
 
 #if defined(CONFIG_USER_ONLY)
-static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
+static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
 {
     if (newsp)
         env->regs[14] = newsp;
@@ -243,21 +269,32 @@ static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
 #define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 #define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 
-#include "cpu-all.h"
-#include "exec-all.h"
+#include "exec/cpu-all.h"
 
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
-    env->pc = tb->pc;
-}
-
-static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
+static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
                                         target_ulong *cs_base, int *flags)
 {
     *pc = env->pc;
     *cs_base = 0;
     *flags = env->dslot |
-            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG));
+            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
+                                    | X_FLAG | PFIX_FLAG));
+}
+
+#define cpu_list cris_cpu_list
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+
+static inline bool cpu_has_work(CPUState *cpu)
+{
+    CPUCRISState *env = &CRIS_CPU(cpu)->env;
+
+    return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 }
 
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
+{
+    env->pc = tb->pc;
+}
 #endif