* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CPU_CRIS_H
#define CPU_CRIS_H
+#include "config.h"
+#include "qemu-common.h"
+
#define TARGET_LONG_BITS 32
-#include "cpu-defs.h"
+#define CPUArchState struct CPUCRISState
+
+#include "exec/cpu-defs.h"
#define TARGET_HAS_ICE 1
#define ELF_MACHINE EM_CRIS
-#define EXCP_MMU_EXEC 0
-#define EXCP_MMU_READ 1
-#define EXCP_MMU_WRITE 2
-#define EXCP_MMU_FLUSH 3
-#define EXCP_MMU_FAULT 4
-#define EXCP_BREAK 16 /* trap. */
+#define EXCP_NMI 1
+#define EXCP_GURU 2
+#define EXCP_BUSFAULT 3
+#define EXCP_IRQ 4
+#define EXCP_BREAK 5
+
+/* CRIS-specific interrupt pending bits. */
+#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* Register aliases. R0 - R15 */
#define R_FP 8
#define PR_WZ 4
#define PR_EXS 5
#define PR_EDA 6
+#define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
#define PR_MOF 7
#define PR_DZ 8
#define PR_EBP 9
#define PR_ERP 10
#define PR_SRP 11
+#define PR_NRP 12
#define PR_CCS 13
#define PR_USP 14
+#define PRV10_BRP 14
#define PR_SPC 15
/* CPU flags. */
+#define Q_FLAG 0x80000000
+#define M_FLAG_V32 0x40000000
+#define PFIX_FLAG 0x800 /* CRISv10 Only. */
+#define F_FLAG_V10 0x400
+#define P_FLAG_V10 0x200
#define S_FLAG 0x200
#define R_FLAG 0x100
#define P_FLAG 0x80
-#define U_FLAG 0x40
-#define P_FLAG 0x80
+#define M_FLAG_V10 0x80
#define U_FLAG 0x40
#define I_FLAG 0x20
#define X_FLAG 0x10
#define CC_A 14
#define CC_P 15
-/* Internal flags for the implementation. */
-#define F_DELAYSLOT 1
-
#define NB_MMU_MODES 2
typedef struct CPUCRISState {
/* P0 - P15 are referred to as special registers in the docs. */
uint32_t pregs[16];
- /* Pseudo register for the PC. Not directly accessable on CRIS. */
+ /* Pseudo register for the PC. Not directly accessible on CRIS. */
uint32_t pc;
/* Pseudo register for the kernel stack. */
uint32_t ksp;
- /* These are setup up by the guest code just before transfering the
- control back to the host. */
- int jmp;
- uint32_t btarget;
+ /* Branch. */
+ int dslot;
int btaken;
+ uint32_t btarget;
/* Condition flag tracking. */
uint32_t cc_op;
uint32_t cc_dest;
uint32_t cc_src;
uint32_t cc_result;
-
/* size of the operation, 1 = byte, 2 = word, 4 = dword. */
int cc_size;
-
- /* Extended arithmetics. */
- int cc_x_live;
+ /* X flag at the time of cc snapshot. */
int cc_x;
- int exception_index;
- int interrupt_request;
+ /* CRIS has certain insns that lockout interrupts. */
+ int locked_irq;
int interrupt_vector;
int fault_vector;
int trap_vector;
- uint32_t debug1;
- uint32_t debug2;
- uint32_t debug3;
-
- struct
- {
- int exec_insns;
- int exec_loads;
- int exec_stores;
- } stats;
-
/* FIXME: add a check in the translator to avoid writing to support
register sets beyond the 4th. The ISA allows up to 256! but in
practice there is no core that implements more than 4.
*/
uint32_t sregs[4][16];
+ /* Linear feedback shift reg in the mmu. Used to provide pseudo
+ randomness for the 'hint' the mmu gives to sw for chosing valid
+ sets on TLB refills. */
+ uint32_t mmu_rand_lfsr;
+
/*
* We just store the stores to the tlbset here for later evaluation
* when the hw needs access to them.
uint32_t lo;
} tlbsets[2][4][16];
- int features;
- int user_mode_only;
- int halted;
-
- jmp_buf jmp_env;
CPU_COMMON
+
+ /* Members after CPU_COMMON are preserved across resets. */
+ void *load_info;
} CPUCRISState;
-CPUCRISState *cpu_cris_init(const char *cpu_model);
+#include "cpu-qom.h"
+
+CRISCPU *cpu_cris_init(const char *cpu_model);
int cpu_cris_exec(CPUCRISState *s);
void cpu_cris_close(CPUCRISState *s);
void do_interrupt(CPUCRISState *env);
is returned if the signal was handled by the virtual CPU. */
int cpu_cris_signal_handler(int host_signum, void *pinfo,
void *puc);
-void cpu_cris_flush_flags(CPUCRISState *, int);
-
-
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi);
enum {
CC_OP_DYNAMIC, /* Use env->cc_op */
CC_OP_FLAGS,
- CC_OP_LOGIC,
CC_OP_CMP,
CC_OP_MOVE,
- CC_OP_MOVE_PD,
- CC_OP_MOVE_SD,
CC_OP_ADD,
CC_OP_ADDC,
CC_OP_MCP,
CC_OP_MULS,
CC_OP_MULU,
CC_OP_DSTEP,
+ CC_OP_MSTEP,
CC_OP_BOUND,
CC_OP_OR,
CC_OP_LZ
};
-#define CCF_C 0x01
-#define CCF_V 0x02
-#define CCF_Z 0x04
-#define CCF_N 0x08
-#define CCF_X 0x10
-
-#define CRIS_SSP 0
-#define CRIS_USP 1
-
-void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
-void cris_set_macsr(CPUCRISState *env, uint32_t val);
-void cris_switch_sp(CPUCRISState *env);
-
-void do_cris_semihosting(CPUCRISState *env, int nr);
+/* CRIS uses 8k pages. */
+#define TARGET_PAGE_BITS 13
+#define MMAP_SHIFT TARGET_PAGE_BITS
-enum cris_features {
- CRIS_FEATURE_CF_ISA_MUL,
-};
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
-static inline int cris_feature(CPUCRISState *env, int feature)
+static inline CPUCRISState *cpu_init(const char *cpu_model)
{
- return (env->features & (1u << feature)) != 0;
+ CRISCPU *cpu = cpu_cris_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
}
-void register_cris_insns (CPUCRISState *env);
-
-/* CRIS uses 8k pages. */
-#define TARGET_PAGE_BITS 13
-#define MMAP_SHIFT TARGET_PAGE_BITS
-
-#define CPUState CPUCRISState
-#define cpu_init cpu_cris_init
#define cpu_exec cpu_cris_exec
#define cpu_gen_code cpu_cris_gen_code
#define cpu_signal_handler cpu_cris_signal_handler
+#define CPU_SAVE_VERSION 1
+
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+static inline int cpu_mmu_index (CPUCRISState *env)
{
return !!(env->pregs[PR_CCS] & U_FLAG);
}
+int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+ int mmu_idx);
+#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
+
+#if defined(CONFIG_USER_ONLY)
+static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
+{
+ if (newsp)
+ env->regs[14] = newsp;
+ env->regs[10] = 0;
+}
+#endif
+
+static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
+{
+ env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
+}
+
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
-#include "cpu-all.h"
+#include "exec/cpu-all.h"
+
+static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->dslot |
+ (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
+ | X_FLAG | PFIX_FLAG));
+}
+
+#define cpu_list cris_cpu_list
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+
+static inline bool cpu_has_work(CPUState *cpu)
+{
+ CPUCRISState *env = &CRIS_CPU(cpu)->env;
+
+ return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec/exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
#endif
projects / qemu.git / blobdiff