target-cris: Move TCG initialization to CRISCPU initfn

[qemu.git] / target-cris / helper.c

diff --git a/target-cris/helper.c b/target-cris/helper.c
index fcdcf977fe24e53d9c7fc3f01b72893860b9cac9..6e75e9819e7eac3b38df3f1559ab68aa5d415528 100644 (file)
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -18,14 +18,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <stdio.h>
-#include <string.h>
-
-#include "config.h"
 #include "cpu.h"
 #include "mmu.h"
-#include "exec-all.h"
-#include "host-utils.h"
+#include "qemu/host-utils.h"
 
 
 //#define CRIS_HELPER_DEBUG
@@ -33,7 +28,7 @@
 
 #ifdef CRIS_HELPER_DEBUG
 #define D(x) x
-#define D_LOG(...) qemu_log(__VA__ARGS__)
+#define D_LOG(...) qemu_log(__VA_ARGS__)
 #else
 #define D(x)
 #define D_LOG(...) do { } while (0)
@@ -41,14 +36,14 @@
 
 #if defined(CONFIG_USER_ONLY)
 
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUCRISState *env)
 {
        env->exception_index = -1;
        env->pregs[PR_ERP] = env->pc;
 }
 
-int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
-                             int mmu_idx, int is_softmmu)
+int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
+                              int mmu_idx)
 {
        env->exception_index = 0xaa;
        env->pregs[PR_EDA] = address;
@@ -59,7 +54,7 @@ int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
 #else /* !CONFIG_USER_ONLY */
 
 
-static void cris_shift_ccs(CPUState *env)
+static void cris_shift_ccs(CPUCRISState *env)
 {
        uint32_t ccs;
        /* Apply the ccs shift.  */
@@ -68,8 +63,8 @@ static void cris_shift_ccs(CPUState *env)
        env->pregs[PR_CCS] = ccs;
 }
 
-int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
-                               int mmu_idx, int is_softmmu)
+int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw,
+                               int mmu_idx)
 {
        struct cris_mmu_result res;
        int prot, miss;
@@ -78,7 +73,7 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 
        D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
        miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
-                                 rw, mmu_idx);
+                                 rw, mmu_idx, 0);
        if (miss)
        {
                if (env->exception_index == EXCP_BUSFAULT)
@@ -101,18 +96,17 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                phy = res.phy & ~0x80000000;
                prot = res.prot;
                tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
-                             prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE);
+                             prot, mmu_idx, TARGET_PAGE_SIZE);
                 r = 0;
        }
        if (r > 0)
-               D_LOG("%s returns %d irqreq=%x addr=%x"
-                         " phy=%x ismmu=%d vec=%x pc=%x\n", 
-                         __func__, r, env->interrupt_request, 
-                         address, res.phy, is_softmmu, res.bf_vec, env->pc);
+            D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
+                  __func__, r, env->interrupt_request, address, res.phy,
+                  res.bf_vec, env->pc);
        return r;
 }
 
-static void do_interruptv10(CPUState *env)
+static void do_interruptv10(CPUCRISState *env)
 {
        int ex_vec = -1;
 
@@ -127,18 +121,18 @@ static void do_interruptv10(CPUState *env)
                        /* These exceptions are genereated by the core itself.
                           ERP should point to the insn following the brk.  */
                        ex_vec = env->trap_vector;
-                       env->pregs[PR_ERP] = env->pc;
+                       env->pregs[PRV10_BRP] = env->pc;
                        break;
 
                case EXCP_NMI:
                        /* NMI is hardwired to vector zero.  */
                        ex_vec = 0;
-                       env->pregs[PR_CCS] &= ~M_FLAG;
-                       env->pregs[PR_NRP] = env->pc;
+                       env->pregs[PR_CCS] &= ~M_FLAG_V10;
+                       env->pregs[PRV10_BRP] = env->pc;
                        break;
 
                case EXCP_BUSFAULT:
-                       assert(0);
+                        cpu_abort(env, "Unhandled busfault");
                        break;
 
                default:
@@ -157,8 +151,9 @@ static void do_interruptv10(CPUState *env)
        }
 
        /* Now that we are in kernel mode, load the handlers address.  */
-       env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+        env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
        env->locked_irq = 1;
+       env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 
        qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", 
                      __func__, env->pc, ex_vec, 
@@ -167,7 +162,7 @@ static void do_interruptv10(CPUState *env)
                      env->pregs[PR_ERP]);
 }
 
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUCRISState *env)
 {
        int ex_vec = -1;
 
@@ -190,7 +185,7 @@ void do_interrupt(CPUState *env)
                case EXCP_NMI:
                        /* NMI is hardwired to vector zero.  */
                        ex_vec = 0;
-                       env->pregs[PR_CCS] &= ~M_FLAG;
+                       env->pregs[PR_CCS] &= ~M_FLAG_V32;
                        env->pregs[PR_NRP] = env->pc;
                        break;
 
@@ -235,8 +230,14 @@ void do_interrupt(CPUState *env)
        /* Apply the CRIS CCS shift. Clears U if set.  */
        cris_shift_ccs(env);
 
-       /* Now that we are in kernel mode, load the handlers address.  */
-       env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
+       /* Now that we are in kernel mode, load the handlers address.
+          This load may not fault, real hw leaves that behaviour as
+          undefined.  */
+        env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
+
+       /* Clear the excption_index to avoid spurios hw_aborts for recursive
+          bus faults.  */
+       env->exception_index = -1;
 
        D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
                   __func__, env->pc, ex_vec,
@@ -245,12 +246,18 @@ void do_interrupt(CPUState *env)
                   env->pregs[PR_ERP]);
 }
 
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
 {
        uint32_t phy = addr;
        struct cris_mmu_result res;
        int miss;
-       miss = cris_mmu_translate(&res, env, addr, 0, 0);
+
+       miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
+       /* If D TLB misses, try I TLB.  */
+       if (miss) {
+               miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
+       }
+
        if (!miss)
                phy = res.phy;
        D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));