* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/*
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
-#include <assert.h>
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "helper.h"
+#include "mmu.h"
#include "crisv32-decode.h"
#include "qemu-common.h"
#define DISAS_CRIS 0
#if DISAS_CRIS
-#define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
+# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
#else
-#define DIS(x)
+# define LOG_DIS(...) do { } while (0)
#endif
#define D(x)
target_ulong pc, ppc;
/* Decoder. */
+ unsigned int (*decoder)(struct DisasContext *dc);
uint32_t ir;
uint32_t opcode;
unsigned int op1;
unsigned int mode;
unsigned int postinc;
+ unsigned int size;
+ unsigned int src;
+ unsigned int dst;
+ unsigned int cond;
+
int update_cc;
int cc_op;
int cc_size;
int flags_x;
int clear_x; /* Clear x after this insn? */
+ int clear_prefix; /* Clear prefix after this insn? */
+ int clear_locked_irq; /* Clear the irq lockout. */
int cpustate_changed;
unsigned int tb_flags; /* tb dependent flags. */
int is_jmp;
-#define JMP_NOJMP 0
-#define JMP_DIRECT 1
-#define JMP_INDIRECT 2
+#define JMP_NOJMP 0
+#define JMP_DIRECT 1
+#define JMP_DIRECT_CC 2
+#define JMP_INDIRECT 3
int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
uint32_t jmp_pc;
static void gen_BUG(DisasContext *dc, const char *file, int line)
{
printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
- fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
+ qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
cpu_abort(dc->env, "%s:%d\n", file, line);
}
tcg_gen_mov_tl(tn, tcg_const_tl(0));
else if (r == PR_VR)
tcg_gen_mov_tl(tn, tcg_const_tl(32));
- else if (r == PR_EDA) {
- printf("read from EDA!\n");
- tcg_gen_mov_tl(tn, cpu_PR[r]);
- }
else
tcg_gen_mov_tl(tn, cpu_PR[r]);
}
}
}
+/* Sign extend at translation time. */
+static int sign_extend(unsigned int val, unsigned int width)
+{
+ int sval;
+
+ /* LSL. */
+ val <<= 31 - width;
+ sval = val;
+ /* ASR. */
+ sval >>= 31 - width;
+ return sval;
+}
+
+static int cris_fetch(DisasContext *dc, uint32_t addr,
+ unsigned int size, unsigned int sign)
+{
+ int r;
+
+ switch (size) {
+ case 4:
+ {
+ r = ldl_code(addr);
+ break;
+ }
+ case 2:
+ {
+ if (sign) {
+ r = ldsw_code(addr);
+ } else {
+ r = lduw_code(addr);
+ }
+ break;
+ }
+ case 1:
+ {
+ if (sign) {
+ r = ldsb_code(addr);
+ } else {
+ r = ldub_code(addr);
+ }
+ break;
+ }
+ default:
+ cpu_abort(dc->env, "Invalid fetch size %d\n", size);
+ break;
+ }
+ return r;
+}
+
+static void cris_lock_irq(DisasContext *dc)
+{
+ dc->clear_locked_irq = 0;
+ t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
+}
+
static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
tcg_temp_free_i64(t1);
}
-/* 32bit branch-free binary search for counting leading zeros. */
-static void t_gen_lz_i32(TCGv d, TCGv x)
-{
- TCGv_i32 y, m, n;
-
- y = tcg_temp_new_i32();
- m = tcg_temp_new_i32();
- n = tcg_temp_new_i32();
-
- /* y = -(x >> 16) */
- tcg_gen_shri_i32(y, x, 16);
- tcg_gen_neg_i32(y, y);
-
- /* m = (y >> 16) & 16 */
- tcg_gen_sari_i32(m, y, 16);
- tcg_gen_andi_i32(m, m, 16);
-
- /* n = 16 - m */
- tcg_gen_sub_i32(n, tcg_const_i32(16), m);
- /* x = x >> m */
- tcg_gen_shr_i32(x, x, m);
-
- /* y = x - 0x100 */
- tcg_gen_subi_i32(y, x, 0x100);
- /* m = (y >> 16) & 8 */
- tcg_gen_sari_i32(m, y, 16);
- tcg_gen_andi_i32(m, m, 8);
- /* n = n + m */
- tcg_gen_add_i32(n, n, m);
- /* x = x << m */
- tcg_gen_shl_i32(x, x, m);
-
- /* y = x - 0x1000 */
- tcg_gen_subi_i32(y, x, 0x1000);
- /* m = (y >> 16) & 4 */
- tcg_gen_sari_i32(m, y, 16);
- tcg_gen_andi_i32(m, m, 4);
- /* n = n + m */
- tcg_gen_add_i32(n, n, m);
- /* x = x << m */
- tcg_gen_shl_i32(x, x, m);
-
- /* y = x - 0x4000 */
- tcg_gen_subi_i32(y, x, 0x4000);
- /* m = (y >> 16) & 2 */
- tcg_gen_sari_i32(m, y, 16);
- tcg_gen_andi_i32(m, m, 2);
- /* n = n + m */
- tcg_gen_add_i32(n, n, m);
- /* x = x << m */
- tcg_gen_shl_i32(x, x, m);
-
- /* y = x >> 14 */
- tcg_gen_shri_i32(y, x, 14);
- /* m = y & ~(y >> 1) */
- tcg_gen_sari_i32(m, y, 1);
- tcg_gen_not_i32(m, m);
- tcg_gen_and_i32(m, m, y);
-
- /* d = n + 2 - m */
- tcg_gen_addi_i32(d, n, 2);
- tcg_gen_sub_i32(d, d, m);
-
- tcg_temp_free(y);
- tcg_temp_free(m);
- tcg_temp_free(n);
-}
-
-static void t_gen_btst(TCGv d, TCGv a, TCGv b)
-{
- TCGv sbit;
- TCGv bset;
- TCGv t0;
- int l1;
-
- /* des ref:
- The N flag is set according to the selected bit in the dest reg.
- The Z flag is set if the selected bit and all bits to the right are
- zero.
- The X flag is cleared.
- Other flags are left untouched.
- The destination reg is not affected.
-
- unsigned int fz, sbit, bset, mask, masked_t0;
-
- sbit = T1 & 31;
- bset = !!(T0 & (1 << sbit));
- mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
- masked_t0 = T0 & mask;
- fz = !(masked_t0 | bset);
-
- // Clear the X, N and Z flags.
- T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
- // Set the N and Z flags accordingly.
- T0 |= (bset << 3) | (fz << 2);
- */
-
- l1 = gen_new_label();
- sbit = tcg_temp_new();
- bset = tcg_temp_new();
- t0 = tcg_temp_new();
-
- /* Compute bset and sbit. */
- tcg_gen_andi_tl(sbit, b, 31);
- tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
- tcg_gen_and_tl(bset, a, t0);
- tcg_gen_shr_tl(bset, bset, sbit);
- /* Displace to N_FLAG. */
- tcg_gen_shli_tl(bset, bset, 3);
-
- tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
- tcg_gen_subi_tl(sbit, sbit, 1);
- tcg_gen_and_tl(sbit, a, sbit);
-
- tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
- /* or in the N_FLAG. */
- tcg_gen_or_tl(d, d, bset);
- tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
- /* or in the Z_FLAG. */
- tcg_gen_ori_tl(d, d, Z_FLAG);
- gen_set_label(l1);
-
- tcg_temp_free(sbit);
- tcg_temp_free(bset);
-}
-
static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
{
int l1;
gen_set_label(l1);
}
+static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
+{
+ TCGv t;
+
+ /*
+ * d <<= 1
+ * if (n)
+ * d += s;
+ */
+ t = tcg_temp_new();
+ tcg_gen_shli_tl(d, a, 1);
+ tcg_gen_shli_tl(t, ccs, 31 - 3);
+ tcg_gen_sari_tl(t, t, 31);
+ tcg_gen_and_tl(t, t, b);
+ tcg_gen_add_tl(d, d, t);
+ tcg_temp_free(t);
+}
+
/* Extended arithmetics on CRIS. */
static inline void t_gen_add_flag(TCGv d, int flag)
{
static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
{
- TCGv btaken;
int l1;
l1 = gen_new_label();
- btaken = tcg_temp_new();
/* Conditional jmp. */
- tcg_gen_mov_tl(btaken, env_btaken);
tcg_gen_mov_tl(env_pc, pc_false);
- tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
tcg_gen_mov_tl(env_pc, pc_true);
gen_set_label(l1);
-
- tcg_temp_free(btaken);
}
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(env_pc, dest);
- tcg_gen_exit_tb((long)tb + n);
+ tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
tcg_gen_movi_tl(env_pc, dest);
tcg_gen_exit_tb(0);
}
}
-/* Sign extend at translation time. */
-static int sign_extend(unsigned int val, unsigned int width)
-{
- int sval;
-
- /* LSL. */
- val <<= 31 - width;
- sval = val;
- /* ASR. */
- sval >>= 31 - width;
- return sval;
-}
-
static inline void cris_clear_x_flag(DisasContext *dc)
{
if (dc->flagx_known && dc->flags_x)
static void cris_evaluate_flags(DisasContext *dc)
{
- if (!dc->flags_uptodate) {
- cris_flush_cc_state(dc);
+ if (dc->flags_uptodate)
+ return;
- switch (dc->cc_op)
+ cris_flush_cc_state(dc);
+
+ switch (dc->cc_op)
+ {
+ case CC_OP_MCP:
+ gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_src,
+ cc_dest, cc_result);
+ break;
+ case CC_OP_MULS:
+ gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_result,
+ cpu_PR[PR_MOF]);
+ break;
+ case CC_OP_MULU:
+ gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_result,
+ cpu_PR[PR_MOF]);
+ break;
+ case CC_OP_MOVE:
+ case CC_OP_AND:
+ case CC_OP_OR:
+ case CC_OP_XOR:
+ case CC_OP_ASR:
+ case CC_OP_LSR:
+ case CC_OP_LSL:
+ switch (dc->cc_size)
{
- case CC_OP_MCP:
- gen_helper_evaluate_flags_mcp();
- break;
- case CC_OP_MULS:
- gen_helper_evaluate_flags_muls();
- break;
- case CC_OP_MULU:
- gen_helper_evaluate_flags_mulu();
- break;
- case CC_OP_MOVE:
- case CC_OP_AND:
- case CC_OP_OR:
- case CC_OP_XOR:
- case CC_OP_ASR:
- case CC_OP_LSR:
- case CC_OP_LSL:
- switch (dc->cc_size)
- {
- case 4:
- gen_helper_evaluate_flags_move_4();
- break;
- case 2:
- gen_helper_evaluate_flags_move_2();
- break;
- default:
- gen_helper_evaluate_flags();
- break;
- }
- break;
- case CC_OP_FLAGS:
- /* live. */
- break;
- default:
- {
- switch (dc->cc_size)
- {
- case 4:
- gen_helper_evaluate_flags_alu_4();
- break;
- default:
- gen_helper_evaluate_flags();
- break;
- }
- }
+ case 4:
+ gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_result);
+ break;
+ case 2:
+ gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_result);
+ break;
+ default:
+ gen_helper_evaluate_flags();
break;
}
- if (dc->flagx_known) {
- if (dc->flags_x)
- tcg_gen_ori_tl(cpu_PR[PR_CCS],
- cpu_PR[PR_CCS], X_FLAG);
- else
- tcg_gen_andi_tl(cpu_PR[PR_CCS],
- cpu_PR[PR_CCS], ~X_FLAG);
- }
+ break;
+ case CC_OP_FLAGS:
+ /* live. */
+ break;
+ case CC_OP_SUB:
+ case CC_OP_CMP:
+ if (dc->cc_size == 4)
+ gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
+ else
+ gen_helper_evaluate_flags();
- dc->flags_uptodate = 1;
+ break;
+ default:
+ switch (dc->cc_size)
+ {
+ case 4:
+ gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
+ break;
+ default:
+ gen_helper_evaluate_flags();
+ break;
+ }
+ break;
}
+
+ if (dc->flagx_known) {
+ if (dc->flags_x)
+ tcg_gen_ori_tl(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], X_FLAG);
+ else if (dc->cc_op == CC_OP_FLAGS)
+ tcg_gen_andi_tl(cpu_PR[PR_CCS],
+ cpu_PR[PR_CCS], ~X_FLAG);
+ }
+ dc->flags_uptodate = 1;
}
static void cris_cc_mask(DisasContext *dc, unsigned int mask)
/* Update cc after executing ALU op. needs the result. */
static inline void cris_update_result(DisasContext *dc, TCGv res)
{
- if (dc->update_cc) {
- if (dc->cc_size == 4 &&
- (dc->cc_op == CC_OP_SUB
- || dc->cc_op == CC_OP_ADD))
- return;
+ if (dc->update_cc)
tcg_gen_mov_tl(cc_result, res);
- }
}
/* Returns one if the write back stage should execute. */
t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
- t_gen_lz_i32(dst, b);
- break;
- case CC_OP_BTST:
- t_gen_btst(dst, a, b);
+ gen_helper_lz(dst, b);
break;
case CC_OP_MULS:
t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
case CC_OP_DSTEP:
t_gen_cris_dstep(dst, a, b);
break;
+ case CC_OP_MSTEP:
+ t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
+ break;
case CC_OP_BOUND:
{
int l1;
t_gen_subx_carry(dc, dst);
break;
default:
- fprintf (logfile, "illegal ALU op.\n");
+ qemu_log("illegal ALU op.\n");
BUG();
break;
}
writeback = 1;
- if (op == CC_OP_BOUND || op == CC_OP_BTST)
- tmp = tcg_temp_local_new();
-
if (op == CC_OP_CMP) {
tmp = tcg_temp_new();
writeback = 0;
case CC_OP_CMP: return 1;
case CC_OP_NEG: return 1;
case CC_OP_OR: return 1;
+ case CC_OP_AND: return 1;
case CC_OP_XOR: return 1;
case CC_OP_MULU: return 1;
case CC_OP_MULS: return 1;
* code is true.
*/
arith_opt = arith_cc(dc) && !dc->flags_uptodate;
- move_opt = (dc->cc_op == CC_OP_MOVE) && dc->flags_uptodate;
+ move_opt = (dc->cc_op == CC_OP_MOVE);
switch (cond) {
case CC_EQ:
- if (arith_opt || move_opt) {
- /* If cc_result is zero, T0 should be
- non-zero otherwise T0 should be zero. */
- int l1;
- l1 = gen_new_label();
- tcg_gen_movi_tl(cc, 0);
- tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
- 0, l1);
- tcg_gen_movi_tl(cc, 1);
- gen_set_label(l1);
+ if ((arith_opt || move_opt)
+ && dc->cc_x_uptodate != (2 | X_FLAG)) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cc,
+ cc_result, tcg_const_tl(0));
}
else {
cris_evaluate_flags(dc);
}
break;
case CC_NE:
- if (arith_opt || move_opt)
+ if ((arith_opt || move_opt)
+ && dc->cc_x_uptodate != (2 | X_FLAG)) {
tcg_gen_mov_tl(cc, cc_result);
- else {
+ } else {
cris_evaluate_flags(dc);
tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
Z_FLAG);
else if (dc->cc_size == 2)
bits = 15;
- tcg_gen_shri_tl(cc, cc_result, 31);
+ tcg_gen_shri_tl(cc, cc_result, bits);
+ tcg_gen_andi_tl(cc, cc, 1);
}
else {
cris_evaluate_flags(dc);
static void cris_store_direct_jmp(DisasContext *dc)
{
/* Store the direct jmp state into the cpu-state. */
- if (dc->jmp == JMP_DIRECT) {
+ if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
+ if (dc->jmp == JMP_DIRECT) {
+ tcg_gen_movi_tl(env_btaken, 1);
+ }
tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
- tcg_gen_movi_tl(env_btaken, 1);
+ dc->jmp = JMP_INDIRECT;
}
}
/* This helps us re-schedule the micro-code to insns in delay-slots
before the actual jump. */
dc->delayed_branch = 2;
+ dc->jmp = JMP_DIRECT_CC;
dc->jmp_pc = dc->pc + offset;
- if (cond != CC_A)
- {
- dc->jmp = JMP_INDIRECT;
- gen_tst_cc (dc, env_btaken, cond);
- tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
- } else {
- /* Allow chaining. */
- dc->jmp = JMP_DIRECT;
- }
+ gen_tst_cc (dc, env_btaken, cond);
+ tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
}
before the actual jump. */
dc->delayed_branch = 2;
dc->jmp = type;
- if (type == JMP_INDIRECT)
+ if (type == JMP_INDIRECT) {
tcg_gen_movi_tl(env_btaken, 1);
+ }
}
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
TCGv dst)
{
- unsigned int rs, rd;
+ unsigned int rs;
uint32_t imm;
int is_imm;
int insn_len = 2;
rs = dc->op1;
- rd = dc->op2;
is_imm = rs == 15 && dc->postinc;
/* Load [$rs] onto T1. */
if (memsize == 1)
insn_len++;
- if (memsize != 4) {
- if (s_ext) {
- if (memsize == 1)
- imm = ldsb_code(dc->pc + 2);
- else
- imm = ldsw_code(dc->pc + 2);
- } else {
- if (memsize == 1)
- imm = ldub_code(dc->pc + 2);
- else
- imm = lduw_code(dc->pc + 2);
- }
- } else
- imm = ldl_code(dc->pc + 2);
-
+ imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
tcg_gen_movi_tl(dst, imm);
dc->postinc = 0;
} else {
/* Start of insn decoders. */
-static unsigned int dec_bccq(DisasContext *dc)
+static int dec_bccq(DisasContext *dc)
{
int32_t offset;
int sign;
uint32_t cond = dc->op2;
- int tmp;
offset = EXTRACT_FIELD (dc->ir, 1, 7);
sign = EXTRACT_FIELD(dc->ir, 0, 0);
offset *= 2;
offset |= sign << 8;
- tmp = offset;
offset = sign_extend(offset, 8);
- DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
+ LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
/* op2 holds the condition-code. */
cris_cc_mask(dc, 0);
cris_prepare_cc_branch (dc, offset, cond);
return 2;
}
-static unsigned int dec_addoq(DisasContext *dc)
+static int dec_addoq(DisasContext *dc)
{
int32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
imm = sign_extend(dc->op1, 7);
- DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
+ LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
cris_cc_mask(dc, 0);
/* Fetch register operand, */
tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
return 2;
}
-static unsigned int dec_addq(DisasContext *dc)
+static int dec_addq(DisasContext *dc)
{
- DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
+ LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
-static unsigned int dec_moveq(DisasContext *dc)
+static int dec_moveq(DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
- DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
+ LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
- tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
+ tcg_gen_movi_tl(cpu_R[dc->op2], imm);
return 2;
}
-static unsigned int dec_subq(DisasContext *dc)
+static int dec_subq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
- DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
+ LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_SUB,
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
-static unsigned int dec_cmpq(DisasContext *dc)
+static int dec_cmpq(DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
- DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
+ LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static unsigned int dec_andq(DisasContext *dc)
+static int dec_andq(DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
- DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
+ LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_AND,
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static unsigned int dec_orq(DisasContext *dc)
+static int dec_orq(DisasContext *dc)
{
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
- DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
+ LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
-static unsigned int dec_btstq(DisasContext *dc)
+static int dec_btstq(DisasContext *dc)
{
- TCGv l0;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
- DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
+ LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
- l0 = tcg_temp_local_new();
- cris_alu(dc, CC_OP_BTST,
- l0, cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
+ cris_evaluate_flags(dc);
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- t_gen_mov_preg_TN(dc, PR_CCS, l0);
dc->flags_uptodate = 1;
- tcg_temp_free(l0);
return 2;
}
-static unsigned int dec_asrq(DisasContext *dc)
+static int dec_asrq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
- DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
+ LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
}
-static unsigned int dec_lslq(DisasContext *dc)
+static int dec_lslq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
- DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
+ LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
}
-static unsigned int dec_lsrq(DisasContext *dc)
+static int dec_lsrq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
- DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
+ LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
return 2;
}
-static unsigned int dec_move_r(DisasContext *dc)
+static int dec_move_r(DisasContext *dc)
{
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("move.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
if (size == 4) {
return 2;
}
-static unsigned int dec_scc_r(DisasContext *dc)
+static int dec_scc_r(DisasContext *dc)
{
int cond = dc->op2;
- DIS(fprintf (logfile, "s%s $r%u\n",
- cc_name(cond), dc->op1));
+ LOG_DIS("s%s $r%u\n",
+ cc_name(cond), dc->op1);
if (cond != CC_A)
{
}
}
-static unsigned int dec_and_r(DisasContext *dc)
+static int dec_and_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("and.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
return 2;
}
-static unsigned int dec_lz_r(DisasContext *dc)
+static int dec_lz_r(DisasContext *dc)
{
TCGv t0;
- DIS(fprintf (logfile, "lz $r%u, $r%u\n",
- dc->op1, dc->op2));
+ LOG_DIS("lz $r%u, $r%u\n",
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
return 2;
}
-static unsigned int dec_lsl_r(DisasContext *dc)
+static int dec_lsl_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("lsl.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
return 2;
}
-static unsigned int dec_lsr_r(DisasContext *dc)
+static int dec_lsr_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("lsr.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
return 2;
}
-static unsigned int dec_asr_r(DisasContext *dc)
+static int dec_asr_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("asr.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
return 2;
}
-static unsigned int dec_muls_r(DisasContext *dc)
+static int dec_muls_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("muls.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZV);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
return 2;
}
-static unsigned int dec_mulu_r(DisasContext *dc)
+static int dec_mulu_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("mulu.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZV);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
}
-static unsigned int dec_dstep_r(DisasContext *dc)
+static int dec_dstep_r(DisasContext *dc)
{
- DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
+ LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_DSTEP,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
return 2;
}
-static unsigned int dec_xor_r(DisasContext *dc)
+static int dec_xor_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("xor.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
BUG_ON(size != 4); /* xor is dword. */
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
return 2;
}
-static unsigned int dec_bound_r(DisasContext *dc)
+static int dec_bound_r(DisasContext *dc)
{
TCGv l0;
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("bound.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
l0 = tcg_temp_local_new();
dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
return 2;
}
-static unsigned int dec_cmp_r(DisasContext *dc)
+static int dec_cmp_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("cmp.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
return 2;
}
-static unsigned int dec_abs_r(DisasContext *dc)
+static int dec_abs_r(DisasContext *dc)
{
TCGv t0;
- DIS(fprintf (logfile, "abs $r%u, $r%u\n",
- dc->op1, dc->op2));
+ LOG_DIS("abs $r%u, $r%u\n",
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
return 2;
}
-static unsigned int dec_add_r(DisasContext *dc)
+static int dec_add_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("add.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
return 2;
}
-static unsigned int dec_addc_r(DisasContext *dc)
+static int dec_addc_r(DisasContext *dc)
{
- DIS(fprintf (logfile, "addc $r%u, $r%u\n",
- dc->op1, dc->op2));
+ LOG_DIS("addc $r%u, $r%u\n",
+ dc->op1, dc->op2);
cris_evaluate_flags(dc);
+ /* Set for this insn. */
+ dc->flagx_known = 1;
+ dc->flags_x = X_FLAG;
+
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_ADDC,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
return 2;
}
-static unsigned int dec_mcp_r(DisasContext *dc)
+static int dec_mcp_r(DisasContext *dc)
{
- DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
- dc->op2, dc->op1));
+ LOG_DIS("mcp $p%u, $r%u\n",
+ dc->op2, dc->op1);
cris_evaluate_flags(dc);
cris_cc_mask(dc, CC_MASK_RNZV);
cris_alu(dc, CC_OP_MCP,
}
#endif
-static unsigned int dec_swap_r(DisasContext *dc)
+static int dec_swap_r(DisasContext *dc)
{
TCGv t0;
#if DISAS_CRIS
char modename[4];
#endif
- DIS(fprintf (logfile, "swap%s $r%u\n",
- swapmode_name(dc->op2, modename), dc->op1));
+ LOG_DIS("swap%s $r%u\n",
+ swapmode_name(dc->op2, modename), dc->op1);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
return 2;
}
-static unsigned int dec_or_r(DisasContext *dc)
+static int dec_or_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("or.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
return 2;
}
-static unsigned int dec_addi_r(DisasContext *dc)
+static int dec_addi_r(DisasContext *dc)
{
TCGv t0;
- DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
- memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
+ LOG_DIS("addi.%c $r%u, $r%u\n",
+ memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
cris_cc_mask(dc, 0);
t0 = tcg_temp_new();
tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
return 2;
}
-static unsigned int dec_addi_acr(DisasContext *dc)
+static int dec_addi_acr(DisasContext *dc)
{
TCGv t0;
- DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
- memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
+ LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
+ memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
cris_cc_mask(dc, 0);
t0 = tcg_temp_new();
tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
return 2;
}
-static unsigned int dec_neg_r(DisasContext *dc)
+static int dec_neg_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("neg.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
return 2;
}
-static unsigned int dec_btst_r(DisasContext *dc)
+static int dec_btst_r(DisasContext *dc)
{
- TCGv l0;
- DIS(fprintf (logfile, "btst $r%u, $r%u\n",
- dc->op1, dc->op2));
+ LOG_DIS("btst $r%u, $r%u\n",
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
-
- l0 = tcg_temp_local_new();
- cris_alu(dc, CC_OP_BTST, l0, cpu_R[dc->op2], cpu_R[dc->op1], 4);
+ cris_evaluate_flags(dc);
+ gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
+ cpu_R[dc->op1], cpu_PR[PR_CCS]);
+ cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
+ cpu_R[dc->op2], cpu_R[dc->op2], 4);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- t_gen_mov_preg_TN(dc, PR_CCS, l0);
dc->flags_uptodate = 1;
- tcg_temp_free(l0);
return 2;
}
-static unsigned int dec_sub_r(DisasContext *dc)
+static int dec_sub_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
- DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
- memsize_char(size), dc->op1, dc->op2));
+ LOG_DIS("sub.%c $r%u, $r%u\n",
+ memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
}
/* Zero extension. From size to dword. */
-static unsigned int dec_movu_r(DisasContext *dc)
+static int dec_movu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
+ LOG_DIS("movu.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
}
/* Sign extension. From size to dword. */
-static unsigned int dec_movs_r(DisasContext *dc)
+static int dec_movs_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
+ LOG_DIS("movs.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
}
/* zero extension. From size to dword. */
-static unsigned int dec_addu_r(DisasContext *dc)
+static int dec_addu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
+ LOG_DIS("addu.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
}
/* Sign extension. From size to dword. */
-static unsigned int dec_adds_r(DisasContext *dc)
+static int dec_adds_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
+ LOG_DIS("adds.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
}
/* Zero extension. From size to dword. */
-static unsigned int dec_subu_r(DisasContext *dc)
+static int dec_subu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
+ LOG_DIS("subu.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
}
/* Sign extension. From size to dword. */
-static unsigned int dec_subs_r(DisasContext *dc)
+static int dec_subs_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
- DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
+ LOG_DIS("subs.%c $r%u, $r%u\n",
memsize_char(size),
- dc->op1, dc->op2));
+ dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
return 2;
}
-static unsigned int dec_setclrf(DisasContext *dc)
+static int dec_setclrf(DisasContext *dc)
{
uint32_t flags;
int set = (~dc->opcode >> 2) & 1;
flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
| EXTRACT_FIELD(dc->ir, 0, 3);
if (set && flags == 0) {
- DIS(fprintf (logfile, "nop\n"));
+ LOG_DIS("nop\n");
return 2;
} else if (!set && (flags & 0x20)) {
- DIS(fprintf (logfile, "di\n"));
+ LOG_DIS("di\n");
}
else {
- DIS(fprintf (logfile, "%sf %x\n",
+ LOG_DIS("%sf %x\n",
set ? "set" : "clr",
- flags));
+ flags);
}
/* User space is not allowed to touch these. Silently ignore. */
dc->flags_x = 0;
}
- /* Break the TB if the P flag changes. */
- if (flags & P_FLAG) {
- if ((set && !(dc->tb_flags & P_FLAG))
- || (!set && (dc->tb_flags & P_FLAG))) {
- tcg_gen_movi_tl(env_pc, dc->pc + 2);
- dc->is_jmp = DISAS_UPDATE;
- dc->cpustate_changed = 1;
- }
+ /* Break the TB if any of the SPI flag changes. */
+ if (flags & (P_FLAG | S_FLAG)) {
+ tcg_gen_movi_tl(env_pc, dc->pc + 2);
+ dc->is_jmp = DISAS_UPDATE;
+ dc->cpustate_changed = 1;
}
- if (flags & S_FLAG) {
+
+ /* For the I flag, only act on posedge. */
+ if ((flags & I_FLAG)) {
+ tcg_gen_movi_tl(env_pc, dc->pc + 2);
+ dc->is_jmp = DISAS_UPDATE;
dc->cpustate_changed = 1;
}
return 2;
}
-static unsigned int dec_move_rs(DisasContext *dc)
+static int dec_move_rs(DisasContext *dc)
{
- DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
+ LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
return 2;
}
-static unsigned int dec_move_sr(DisasContext *dc)
+static int dec_move_sr(DisasContext *dc)
{
- DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
+ LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
return 2;
}
-static unsigned int dec_move_rp(DisasContext *dc)
+static int dec_move_rp(DisasContext *dc)
{
TCGv t[2];
- DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
+ LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
t[0] = tcg_temp_new();
tcg_temp_free(t[0]);
return 2;
}
-static unsigned int dec_move_pr(DisasContext *dc)
+static int dec_move_pr(DisasContext *dc)
{
TCGv t0;
- DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
+ LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
if (dc->op2 == PR_CCS)
cris_evaluate_flags(dc);
- t0 = tcg_temp_new();
- t_gen_mov_TN_preg(t0, dc->op2);
- cris_alu(dc, CC_OP_MOVE,
- cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]);
- tcg_temp_free(t0);
+ if (dc->op2 == PR_DZ) {
+ tcg_gen_movi_tl(cpu_R[dc->op1], 0);
+ } else {
+ t0 = tcg_temp_new();
+ t_gen_mov_TN_preg(t0, dc->op2);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op1], cpu_R[dc->op1], t0,
+ preg_sizes[dc->op2]);
+ tcg_temp_free(t0);
+ }
return 2;
}
-static unsigned int dec_move_mr(DisasContext *dc)
+static int dec_move_mr(DisasContext *dc)
{
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
+ LOG_DIS("move.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
if (memsize == 4) {
insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
tcg_temp_free(t[1]);
}
-static unsigned int dec_movs_m(DisasContext *dc)
+static int dec_movs_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
+ LOG_DIS("movs.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
return insn_len;
}
-static unsigned int dec_addu_m(DisasContext *dc)
+static int dec_addu_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
+ LOG_DIS("addu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
return insn_len;
}
-static unsigned int dec_adds_m(DisasContext *dc)
+static int dec_adds_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
+ LOG_DIS("adds.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
return insn_len;
}
-static unsigned int dec_subu_m(DisasContext *dc)
+static int dec_subu_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
+ LOG_DIS("subu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
return insn_len;
}
-static unsigned int dec_subs_m(DisasContext *dc)
+static int dec_subs_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
+ LOG_DIS("subs.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
return insn_len;
}
-static unsigned int dec_movu_m(DisasContext *dc)
+static int dec_movu_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
+ LOG_DIS("movu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_cmpu_m(DisasContext *dc)
+static int dec_cmpu_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
+ LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_cmps_m(DisasContext *dc)
+static int dec_cmps_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
- DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
+ LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_cmp_m(DisasContext *dc)
+static int dec_cmp_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
+ LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_test_m(DisasContext *dc)
+static int dec_test_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
+ LOG_DIS("test.%c [$r%u%s] op2=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_evaluate_flags(dc);
return insn_len;
}
-static unsigned int dec_and_m(DisasContext *dc)
+static int dec_and_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
+ LOG_DIS("and.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_add_m(DisasContext *dc)
+static int dec_add_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
+ LOG_DIS("add.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_addo_m(DisasContext *dc)
+static int dec_addo_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
+ LOG_DIS("add.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_bound_m(DisasContext *dc)
+static int dec_bound_m(DisasContext *dc)
{
TCGv l[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
+ LOG_DIS("bound.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
l[0] = tcg_temp_local_new();
l[1] = tcg_temp_local_new();
return insn_len;
}
-static unsigned int dec_addc_mr(DisasContext *dc)
+static int dec_addc_mr(DisasContext *dc)
{
TCGv t[2];
int insn_len = 2;
- DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
+ LOG_DIS("addc [$r%u%s, $r%u\n",
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_evaluate_flags(dc);
+
+ /* Set for this insn. */
+ dc->flagx_known = 1;
+ dc->flags_x = X_FLAG;
+
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
cris_cc_mask(dc, CC_MASK_NZVC);
return insn_len;
}
-static unsigned int dec_sub_m(DisasContext *dc)
+static int dec_sub_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
+ LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2, dc->ir, dc->zzsize));
+ dc->op2, dc->ir, dc->zzsize);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_or_m(DisasContext *dc)
+static int dec_or_m(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
- DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
+ LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
- dc->op2, dc->pc));
+ dc->op2, dc->pc);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_move_mp(DisasContext *dc)
+static int dec_move_mp(DisasContext *dc)
{
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len = 2;
- DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
+ LOG_DIS("move.%c [$r%u%s, $p%u\n",
memsize_char(memsize),
dc->op1,
dc->postinc ? "+]" : "]",
- dc->op2));
+ dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
return insn_len;
}
-static unsigned int dec_move_pm(DisasContext *dc)
+static int dec_move_pm(DisasContext *dc)
{
TCGv t0;
int memsize;
memsize = preg_sizes[dc->op2];
- DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
+ LOG_DIS("move.%c $p%u, [$r%u%s\n",
memsize_char(memsize),
- dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
+ dc->op2, dc->op1, dc->postinc ? "+]" : "]");
/* prepare store. Address in T0, value in T1. */
if (dc->op2 == PR_CCS)
return 2;
}
-static unsigned int dec_movem_mr(DisasContext *dc)
+static int dec_movem_mr(DisasContext *dc)
{
TCGv_i64 tmp[16];
TCGv tmp32;
int i;
int nr = dc->op2 + 1;
- DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
- dc->postinc ? "+]" : "]", dc->op2));
+ LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
+ dc->postinc ? "+]" : "]", dc->op2);
addr = tcg_temp_new();
/* There are probably better ways of doing this. */
tmp32 = tcg_temp_new_i32();
tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
gen_load(dc, tmp32, addr, 4, 0);
- }
+ } else
+ TCGV_UNUSED(tmp32);
tcg_temp_free(addr);
for (i = 0; i < (nr >> 1); i++) {
return 2;
}
-static unsigned int dec_movem_rm(DisasContext *dc)
+static int dec_movem_rm(DisasContext *dc)
{
TCGv tmp;
TCGv addr;
int i;
- DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
- dc->postinc ? "+]" : "]"));
+ LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
+ dc->postinc ? "+]" : "]");
cris_flush_cc_state(dc);
return 2;
}
-static unsigned int dec_move_rm(DisasContext *dc)
+static int dec_move_rm(DisasContext *dc)
{
int memsize;
memsize = memsize_zz(dc);
- DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
- memsize, dc->op2, dc->op1));
+ LOG_DIS("move.%c $r%u, [$r%u]\n",
+ memsize_char(memsize), dc->op2, dc->op1);
/* prepare store. */
cris_flush_cc_state(dc);
return 2;
}
-static unsigned int dec_lapcq(DisasContext *dc)
+static int dec_lapcq(DisasContext *dc)
{
- DIS(fprintf (logfile, "lapcq %x, $r%u\n",
- dc->pc + dc->op1*2, dc->op2));
+ LOG_DIS("lapcq %x, $r%u\n",
+ dc->pc + dc->op1*2, dc->op2);
cris_cc_mask(dc, 0);
tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
return 2;
}
-static unsigned int dec_lapc_im(DisasContext *dc)
+static int dec_lapc_im(DisasContext *dc)
{
unsigned int rd;
int32_t imm;
rd = dc->op2;
cris_cc_mask(dc, 0);
- imm = ldl_code(dc->pc + 2);
- DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
+ imm = cris_fetch(dc, dc->pc + 2, 4, 0);
+ LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
pc = dc->pc;
pc += imm;
- t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
+ tcg_gen_movi_tl(cpu_R[rd], pc);
return 6;
}
/* Jump to special reg. */
-static unsigned int dec_jump_p(DisasContext *dc)
+static int dec_jump_p(DisasContext *dc)
{
- DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
+ LOG_DIS("jump $p%u\n", dc->op2);
if (dc->op2 == PR_CCS)
cris_evaluate_flags(dc);
}
/* Jump and save. */
-static unsigned int dec_jas_r(DisasContext *dc)
+static int dec_jas_r(DisasContext *dc)
{
- DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
+ LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
return 2;
}
-static unsigned int dec_jas_im(DisasContext *dc)
+static int dec_jas_im(DisasContext *dc)
{
uint32_t imm;
- imm = ldl_code(dc->pc + 2);
+ imm = cris_fetch(dc, dc->pc + 2, 4, 0);
- DIS(fprintf (logfile, "jas 0x%x\n", imm));
+ LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
return 6;
}
-static unsigned int dec_jasc_im(DisasContext *dc)
+static int dec_jasc_im(DisasContext *dc)
{
uint32_t imm;
- imm = ldl_code(dc->pc + 2);
+ imm = cris_fetch(dc, dc->pc + 2, 4, 0);
- DIS(fprintf (logfile, "jasc 0x%x\n", imm));
+ LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
return 6;
}
-static unsigned int dec_jasc_r(DisasContext *dc)
+static int dec_jasc_r(DisasContext *dc)
{
- DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
+ LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
return 2;
}
-static unsigned int dec_bcc_im(DisasContext *dc)
+static int dec_bcc_im(DisasContext *dc)
{
int32_t offset;
uint32_t cond = dc->op2;
- offset = ldsw_code(dc->pc + 2);
+ offset = cris_fetch(dc, dc->pc + 2, 2, 1);
- DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
+ LOG_DIS("b%s %d pc=%x dst=%x\n",
cc_name(cond), offset,
- dc->pc, dc->pc + offset));
+ dc->pc, dc->pc + offset);
cris_cc_mask(dc, 0);
/* op2 holds the condition-code. */
return 4;
}
-static unsigned int dec_bas_im(DisasContext *dc)
+static int dec_bas_im(DisasContext *dc)
{
int32_t simm;
- simm = ldl_code(dc->pc + 2);
+ simm = cris_fetch(dc, dc->pc + 2, 4, 0);
- DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
+ LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
return 6;
}
-static unsigned int dec_basc_im(DisasContext *dc)
+static int dec_basc_im(DisasContext *dc)
{
int32_t simm;
- simm = ldl_code(dc->pc + 2);
+ simm = cris_fetch(dc, dc->pc + 2, 4, 0);
- DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
+ LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
return 6;
}
-static unsigned int dec_rfe_etc(DisasContext *dc)
+static int dec_rfe_etc(DisasContext *dc)
{
cris_cc_mask(dc, 0);
- if (dc->op2 == 15) /* ignore halt. */
+ if (dc->op2 == 15) {
+ t_gen_mov_env_TN(halted, tcg_const_tl(1));
+ tcg_gen_movi_tl(env_pc, dc->pc + 2);
+ t_gen_raise_exception(EXCP_HLT);
return 2;
+ }
switch (dc->op2 & 7) {
case 2:
/* rfe. */
- DIS(fprintf(logfile, "rfe\n"));
+ LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
gen_helper_rfe();
dc->is_jmp = DISAS_UPDATE;
break;
case 5:
/* rfn. */
- DIS(fprintf(logfile, "rfn\n"));
+ LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
gen_helper_rfn();
dc->is_jmp = DISAS_UPDATE;
break;
case 6:
- DIS(fprintf(logfile, "break %d\n", dc->op1));
+ LOG_DIS("break %d\n", dc->op1);
cris_evaluate_flags (dc);
/* break. */
tcg_gen_movi_tl(env_pc, dc->pc + 2);
return 2;
}
-static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
+static int dec_ftag_fidx_d_m(DisasContext *dc)
{
return 2;
}
-static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
+static int dec_ftag_fidx_i_m(DisasContext *dc)
{
return 2;
}
-static unsigned int dec_null(DisasContext *dc)
+static int dec_null(DisasContext *dc)
{
printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
dc->pc, dc->opcode, dc->op1, dc->op2);
uint32_t bits;
uint32_t mask;
};
- unsigned int (*dec)(DisasContext *dc);
+ int (*dec)(DisasContext *dc);
} decinfo[] = {
/* Order matters here. */
{DEC_MOVEQ, dec_moveq},
{{0, 0}, dec_null}
};
-static inline unsigned int
-cris_decoder(DisasContext *dc)
+static unsigned int crisv32_decoder(DisasContext *dc)
{
- unsigned int insn_len = 2;
+ int insn_len = 2;
int i;
- if (unlikely(loglevel & CPU_LOG_TB_OP))
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
- dc->ir = lduw_code(dc->pc);
+ dc->ir = cris_fetch(dc, dc->pc, 2, 0);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
{
CPUBreakpoint *bp;
- if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
- TAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
+ QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
if (bp->pc == dc->pc) {
cris_evaluate_flags (dc);
tcg_gen_movi_tl(env_pc, dc->pc);
}
}
+#include "translate_v10.c"
/*
* Delay slots on QEMU/CRIS.
int num_insns;
int max_insns;
- if (!logfile)
- logfile = stderr;
+ qemu_log_try_set_file(stderr);
+
+ if (env->pregs[PR_VR] == 32) {
+ dc->decoder = crisv32_decoder;
+ dc->clear_locked_irq = 0;
+ } else {
+ dc->decoder = crisv10_decoder;
+ dc->clear_locked_irq = 1;
+ }
/* Odd PC indicates that branch is rexecuting due to exception in the
* delayslot, like in real hw.
dc->cc_x_uptodate = 0;
dc->cc_mask = 0;
dc->update_cc = 0;
+ dc->clear_prefix = 0;
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
dc->cc_size_uptodate = -1;
/* Decode TB flags. */
- dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
+ dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
+ | X_FLAG | PFIX_FLAG);
dc->delayed_branch = !!(tb->flags & 7);
if (dc->delayed_branch)
dc->jmp = JMP_INDIRECT;
dc->cpustate_changed = 0;
- if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile,
- "srch=%d pc=%x %x flg=%llx bt=%x ds=%u ccs=%x\n"
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log(
+ "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
"pid=%x usp=%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n",
search_pc, dc->pc, dc->ppc,
- (unsigned long long)tb->flags,
+ (uint64_t)tb->flags,
env->btarget, (unsigned)tb->flags & 7,
env->pregs[PR_CCS],
env->pregs[PR_PID], env->pregs[PR_USP],
env->regs[10], env->regs[11],
env->regs[12], env->regs[13],
env->regs[14], env->regs[15]);
- fprintf(logfile, "--------------\n");
- fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
+ qemu_log("--------------\n");
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
}
/* Pretty disas. */
- DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
+ LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
dc->clear_x = 1;
- insn_len = cris_decoder(dc);
+ insn_len = dc->decoder(dc);
dc->ppc = dc->pc;
dc->pc += insn_len;
if (dc->clear_x)
if (tb->flags & 7)
t_gen_mov_env_TN(dslot,
tcg_const_tl(0));
- if (dc->jmp == JMP_DIRECT) {
- dc->is_jmp = DISAS_NEXT;
+ if (dc->cpustate_changed || !dc->flagx_known
+ || (dc->flags_x != (tb->flags & X_FLAG))) {
+ cris_store_direct_jmp(dc);
+ }
+
+ if (dc->clear_locked_irq) {
+ dc->clear_locked_irq = 0;
+ t_gen_mov_env_TN(locked_irq,
+ tcg_const_tl(0));
+ }
+
+ if (dc->jmp == JMP_DIRECT_CC) {
+ int l1;
+
+ l1 = gen_new_label();
+ cris_evaluate_flags(dc);
+
+ /* Conditional jmp. */
+ tcg_gen_brcondi_tl(TCG_COND_EQ,
+ env_btaken, 0, l1);
+ gen_goto_tb(dc, 1, dc->jmp_pc);
+ gen_set_label(l1);
+ gen_goto_tb(dc, 0, dc->pc);
+ dc->is_jmp = DISAS_TB_JUMP;
+ dc->jmp = JMP_NOJMP;
+ } else if (dc->jmp == JMP_DIRECT) {
+ cris_evaluate_flags(dc);
+ gen_goto_tb(dc, 0, dc->jmp_pc);
+ dc->is_jmp = DISAS_TB_JUMP;
+ dc->jmp = JMP_NOJMP;
} else {
t_gen_cc_jmp(env_btarget,
tcg_const_tl(dc->pc));
break;
} while (!dc->is_jmp && !dc->cpustate_changed
&& gen_opc_ptr < gen_opc_end
+ && !singlestep
&& (dc->pc < next_page_start)
&& num_insns < max_insns);
+ if (dc->clear_locked_irq)
+ t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
+
npc = dc->pc;
- if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
- npc = dc->jmp_pc;
if (tb->cflags & CF_LAST_IO)
gen_io_end();
#ifdef DEBUG_DISAS
#if !DISAS_CRIS
- if (loglevel & CPU_LOG_TB_IN_ASM) {
- target_disas(logfile, pc_start, dc->pc - pc_start, 0);
- fprintf(logfile, "\nisize=%d osize=%zd\n",
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ log_target_disas(pc_start, dc->pc - pc_start,
+ dc->env->pregs[PR_VR]);
+ qemu_log("\nisize=%d osize=%td\n",
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
}
#endif
gen_intermediate_code_internal(env, tb, 1);
}
-void cpu_dump_state (CPUState *env, FILE *f,
- int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
for (i = 0; i < 16; i++) {
- cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
+ cpu_fprintf(f, "%s=%8.8x ",regnames[i], env->regs[i]);
if ((i + 1) % 4 == 0)
cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "\nspecial regs:\n");
for (i = 0; i < 16; i++) {
- cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
+ cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
if ((i + 1) % 4 == 0)
cpu_fprintf(f, "\n");
}
}
+struct
+{
+ uint32_t vr;
+ const char *name;
+} cris_cores[] = {
+ {8, "crisv8"},
+ {9, "crisv9"},
+ {10, "crisv10"},
+ {11, "crisv11"},
+ {32, "crisv32"},
+};
+
+void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ unsigned int i;
+
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
+ (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
+ }
+}
+
+static uint32_t vr_by_name(const char *name)
+{
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
+ if (strcmp(name, cris_cores[i].name) == 0) {
+ return cris_cores[i].vr;
+ }
+ }
+ return 32;
+}
+
CPUCRISState *cpu_cris_init (const char *cpu_model)
{
CPUCRISState *env;
int i;
env = qemu_mallocz(sizeof(CPUCRISState));
- if (!env)
- return NULL;
+ env->pregs[PR_VR] = vr_by_name(cpu_model);
cpu_exec_init(env);
cpu_reset(env);
+ qemu_init_vcpu(env);
if (tcg_initialized)
return env;
tcg_initialized = 1;
+#define GEN_HELPER 2
+#include "helper.h"
+
+ if (env->pregs[PR_VR] < 32) {
+ cpu_crisv10_init(env);
+ return env;
+ }
+
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cc_x = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUState, cc_x), "cc_x");
pregnames[i]);
}
-#define GEN_HELPER 2
-#include "helper.h"
-
return env;
}
void cpu_reset (CPUCRISState *env)
{
+ uint32_t vr;
+
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, breakpoints));
+ env->pregs[PR_VR] = vr;
tlb_flush(env, 1);
- env->pregs[PR_VR] = 32;
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
- env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
+ env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
#else
+ cris_mmu_init(env);
env->pregs[PR_CCS] = 0;
#endif
}
-void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
- unsigned long searched_pc, int pc_pos, void *puc)
+void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
}
projects / qemu.git / blobdiff