if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
if (is_right) {
tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
} else {
tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
#define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
#define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
#define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
+#define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
+ CPUID_EXT_PCLMULQDQ }
+#define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
static const struct SSEOpHelper_epp sse_op_table6[256] = {
[0x00] = SSSE3_OP(pshufb),
[0x3f] = SSE41_OP(pmaxud),
[0x40] = SSE41_OP(pmulld),
[0x41] = SSE41_OP(phminposuw),
+ [0xdb] = AESNI_OP(aesimc),
+ [0xdc] = AESNI_OP(aesenc),
+ [0xdd] = AESNI_OP(aesenclast),
+ [0xde] = AESNI_OP(aesdec),
+ [0xdf] = AESNI_OP(aesdeclast),
};
static const struct SSEOpHelper_eppi sse_op_table7[256] = {
[0x40] = SSE41_OP(dpps),
[0x41] = SSE41_OP(dppd),
[0x42] = SSE41_OP(mpsadbw),
+ [0x44] = PCLMULQDQ_OP(pclmulqdq),
[0x60] = SSE42_OP(pcmpestrm),
[0x61] = SSE42_OP(pcmpestri),
[0x62] = SSE42_OP(pcmpistrm),
[0x63] = SSE42_OP(pcmpistri),
+ [0xdf] = AESNI_OP(aeskeygenassist),
};
static void gen_sse(CPUX86State *env, DisasContext *s, int b,
ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
switch (ot) {
- TCGv_i64 t0, t1;
default:
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
-#ifdef TARGET_X86_64
- tcg_gen_ext32u_i64(t0, cpu_T[0]);
- tcg_gen_ext32u_i64(t1, cpu_regs[R_EDX]);
-#else
- tcg_gen_extu_i32_i64(t0, cpu_T[0]);
- tcg_gen_extu_i32_i64(t0, cpu_regs[R_EDX]);
-#endif
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_trunc_i64_tl(cpu_T[0], t0);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_tl(cpu_T[1], t0);
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
- gen_op_mov_reg_T0(OT_LONG, s->vex_v);
- gen_op_mov_reg_T1(OT_LONG, reg);
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EDX]);
+ tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
+ cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp3_i32);
break;
#ifdef TARGET_X86_64
case OT_QUAD:
- tcg_gen_mov_tl(cpu_T[1], cpu_regs[R_EDX]);
- tcg_gen_mul_tl(cpu_regs[s->vex_v], cpu_T[0], cpu_T[1]);
- gen_helper_umulh(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
+ cpu_T[0], cpu_regs[R_EDX]);
break;
#endif
}
if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_ADX)) {
goto illegal_op;
} else {
- TCGv carry_in, carry_out;
+ TCGv carry_in, carry_out, zero;
int end_op;
ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
carry_in = carry_out;
break;
default:
- end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADCOX);
+ end_op = (b == 0x1f6 ? CC_OP_ADCX : CC_OP_ADOX);
break;
}
/* If we can't reuse carry-out, get it out of EFLAGS. */
#endif
default:
/* Otherwise compute the carry-out in two steps. */
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_regs[reg]);
- tcg_gen_setcond_tl(TCG_COND_LTU, cpu_tmp4,
- cpu_T[0], cpu_regs[reg]);
- tcg_gen_add_tl(cpu_regs[reg], cpu_T[0], carry_in);
- tcg_gen_setcond_tl(TCG_COND_LTU, carry_out,
- cpu_regs[reg], cpu_T[0]);
- tcg_gen_or_tl(carry_out, carry_out, cpu_tmp4);
+ zero = tcg_const_tl(0);
+ tcg_gen_add2_tl(cpu_T[0], carry_out,
+ cpu_T[0], zero,
+ carry_in, zero);
+ tcg_gen_add2_tl(cpu_regs[reg], carry_out,
+ cpu_regs[reg], carry_out,
+ cpu_T[0], zero);
+ tcg_temp_free(zero);
break;
}
- /* We began with all flags computed to CC_SRC, and we
- have now placed the carry-out in CC_DST. All that
- is left is to record the CC_OP. */
set_cc_op(s, end_op);
}
break;
if (mod == 3)
gen_op_mov_TN_reg(OT_LONG, 0, rm);
else
- tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
+ tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
(s->mem_index >> 2) - 1);
- tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
+ tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
case 0x21: /* insertps */
}
s->pc = pc_start;
prefixes = 0;
- aflag = s->code32;
- dflag = s->code32;
s->override = -1;
rex_w = -1;
rex_r = 0;
}
s->pc++;
- /* 4.1.1-4.1.3: No preceeding lock, 66, f2, f3, or rex prefixes. */
+ /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
| PREFIX_LOCK | PREFIX_DATA)) {
goto illegal_op;
}
/* Post-process prefixes. */
- if (prefixes & PREFIX_DATA) {
- dflag ^= 1;
- }
- if (prefixes & PREFIX_ADR) {
- aflag ^= 1;
- }
-#ifdef TARGET_X86_64
if (CODE64(s)) {
- if (rex_w == 1) {
- /* 0x66 is ignored if rex.w is set */
- dflag = 2;
+ /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
+ data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
+ over 0x66 if both are present. */
+ dflag = (rex_w > 0 ? 2 : prefixes & PREFIX_DATA ? 0 : 1);
+ /* In 64-bit mode, 0x67 selects 32-bit addressing. */
+ aflag = (prefixes & PREFIX_ADR ? 1 : 2);
+ } else {
+ /* In 16/32-bit mode, 0x66 selects the opposite data size. */
+ dflag = s->code32;
+ if (prefixes & PREFIX_DATA) {
+ dflag ^= 1;
}
- if (!(prefixes & PREFIX_ADR)) {
- aflag = 2;
+ /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
+ aflag = s->code32;
+ if (prefixes & PREFIX_ADR) {
+ aflag ^= 1;
}
}
-#endif
s->prefix = prefixes;
s->aflag = aflag;
break;
default:
case OT_LONG:
-#ifdef TARGET_X86_64
- gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
- tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
-#else
- {
- TCGv_i64 t0, t1;
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
- tcg_gen_extu_i32_i64(t0, cpu_T[0]);
- tcg_gen_extu_i32_i64(t1, cpu_T[1]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_trunc_i64_i32(cpu_T[0], t0);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_i32(cpu_T[0], t0);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
- tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
- }
-#endif
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
+ tcg_gen_mulu2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
+ cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case OT_QUAD:
- gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]);
+ tcg_gen_mulu2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
+ cpu_T[0], cpu_regs[R_EAX]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
break;
default:
case OT_LONG:
-#ifdef TARGET_X86_64
- gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
-#else
- {
- TCGv_i64 t0, t1;
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
- tcg_gen_ext_i32_i64(t0, cpu_T[0]);
- tcg_gen_ext_i32_i64(t1, cpu_T[1]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_trunc_i64_i32(cpu_T[0], t0);
- gen_op_mov_reg_T0(OT_LONG, R_EAX);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_i32(cpu_T[0], t0);
- gen_op_mov_reg_T0(OT_LONG, R_EDX);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
- }
-#endif
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_regs[R_EAX]);
+ tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
+ cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[R_EAX], cpu_tmp2_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[R_EDX], cpu_tmp3_i32);
+ tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
+ tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
set_cc_op(s, CC_OP_MULL);
break;
#ifdef TARGET_X86_64
case OT_QUAD:
- gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]);
+ tcg_gen_muls2_i64(cpu_regs[R_EAX], cpu_regs[R_EDX],
+ cpu_T[0], cpu_regs[R_EAX]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[R_EAX]);
+ tcg_gen_sari_tl(cpu_cc_src, cpu_regs[R_EAX], 63);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_regs[R_EDX]);
set_cc_op(s, CC_OP_MULQ);
break;
#endif
} else {
gen_op_mov_TN_reg(ot, 1, reg);
}
-
-#ifdef TARGET_X86_64
- if (ot == OT_QUAD) {
- gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
- } else
-#endif
- if (ot == OT_LONG) {
+ switch (ot) {
#ifdef TARGET_X86_64
- tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
- tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
- tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
-#else
- {
- TCGv_i64 t0, t1;
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(t0, cpu_T[0]);
- tcg_gen_ext_i32_i64(t1, cpu_T[1]);
- tcg_gen_mul_i64(t0, t0, t1);
- tcg_gen_trunc_i64_i32(cpu_T[0], t0);
- tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
- tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_i32(cpu_T[1], t0);
- tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
- }
+ case OT_QUAD:
+ tcg_gen_muls2_i64(cpu_regs[reg], cpu_T[1], cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
+ tcg_gen_sari_tl(cpu_cc_src, cpu_cc_dst, 63);
+ tcg_gen_sub_tl(cpu_cc_src, cpu_cc_src, cpu_T[1]);
+ break;
#endif
- } else {
+ case OT_LONG:
+ tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
+ tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
+ tcg_gen_muls2_i32(cpu_tmp2_i32, cpu_tmp3_i32,
+ cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_regs[reg], cpu_tmp2_i32);
+ tcg_gen_sari_i32(cpu_tmp2_i32, cpu_tmp2_i32, 31);
+ tcg_gen_mov_tl(cpu_cc_dst, cpu_regs[reg]);
+ tcg_gen_sub_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
+ tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
+ break;
+ default:
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
/* XXX: use 32 bit mul which could be faster */
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
+ gen_op_mov_reg_T0(ot, reg);
+ break;
}
- gen_op_mov_reg_T0(ot, reg);
set_cc_op(s, CC_OP_MULB + ot);
break;
case 0x1c0:
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline void gen_intermediate_code_internal(CPUX86State *env,
+static inline void gen_intermediate_code_internal(X86CPU *cpu,
TranslationBlock *tb,
- int search_pc)
+ bool search_pc)
{
+ CPUState *cs = CPU(cpu);
+ CPUX86State *env = &cpu->env;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint16_t *gen_opc_end;
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = cs->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
dc->cs_base = cs_base;
if (flags & HF_SOFTMMU_MASK) {
dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
}
- dc->cpuid_features = env->cpuid_features;
- dc->cpuid_ext_features = env->cpuid_ext_features;
- dc->cpuid_ext2_features = env->cpuid_ext2_features;
- dc->cpuid_ext3_features = env->cpuid_ext3_features;
- dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features;
+ dc->cpuid_features = env->features[FEAT_1_EDX];
+ dc->cpuid_ext_features = env->features[FEAT_1_ECX];
+ dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
+ dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
+ dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
#ifdef TARGET_X86_64
dc->lma = (flags >> HF_LMA_SHIFT) & 1;
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_icount_start();
+ gen_tb_start();
for(;;) {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- gen_icount_end(tb, num_insns);
+ gen_tb_end(tb, num_insns);
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
/* we don't forget to fill the last values */
if (search_pc) {
void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 0);
+ gen_intermediate_code_internal(x86_env_get_cpu(env), tb, false);
}
void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 1);
+ gen_intermediate_code_internal(x86_env_get_cpu(env), tb, true);
}
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
projects / qemu.git / blobdiff