#include <inttypes.h>
#include <signal.h>
#include <assert.h>
-#include <sys/mman.h>
#include "cpu.h"
#include "exec-all.h"
int singlestep_enabled; /* "hardware" single step enabled */
int jmp_opt; /* use direct block chaining for direct jumps */
int mem_index; /* select memory access functions */
+ int flags; /* all execution flags */
struct TranslationBlock *tb;
int popl_esp_hack; /* for correct popl with esp base handling */
} DisasContext;
},
static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
- DEF_ARITHC()
+ DEF_ARITHC( )
};
static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[9][2] = {
static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
- DEF_CMPXCHG()
+ DEF_CMPXCHG( )
};
static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[9] = {
},
static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
- DEF_SHIFT()
+ DEF_SHIFT( )
};
static GenOpFunc *gen_op_shift_mem_T0_T1_cc[9][8] = {
gen_op_decl_ECX,
};
-static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
+#ifdef USE_DIRECT_JUMP
+typedef GenOpFunc GenOpFuncTB2;
+#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot]()
+#else
+typedef GenOpFunc1 GenOpFuncTB2;
+#define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot](tb)
+#endif
+
+static GenOpFuncTB2 *gen_op_string_jnz_sub2[2][3] = {
{
gen_op_string_jnz_subb,
gen_op_string_jnz_subw,
if (!s->jmp_opt) \
gen_op_string_jnz_sub_im[nz][ot](next_eip); \
else \
- gen_op_string_jnz_sub[nz][ot]((long)s->tb); \
+ gen_op_string_jnz_sub(nz, ot, (long)s->tb); \
if (!s->jmp_opt) \
gen_op_jz_ecx_im[s->aflag](next_eip); \
gen_jmp(s, cur_eip); \
gen_op_set_cc_op(s->cc_op);
gen_op_jmp_im(cur_eip);
gen_op_movl_seg_T0(seg_reg);
+ /* abort translation because the addseg value may change or
+ because ss32 may change. For R_SS, translation must always
+ stop as a special handling must be done to disable hardware
+ interrupts for the next instruction */
+ if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
+ s->is_jmp = 3;
} else {
gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
+ if (seg_reg == R_SS)
+ s->is_jmp = 3;
}
- /* abort translation because the register may have a non zero base
- or because ss32 may change. For R_SS, translation must always
- stop as a special handling must be done to disable hardware
- interrupts for the next instruction */
- if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
- s->is_jmp = 3;
}
static inline void gen_stack_update(DisasContext *s, int addend)
case 0x80: /* GRP1 */
case 0x81:
+ case 0x82:
case 0x83:
{
int val;
default:
case 0x80:
case 0x81:
+ case 0x82:
val = insn_get(s, ot);
break;
case 0x83:
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_op_jmp_im(pc_start - s->cs_base);
- gen_op_ljmp_protected_T0_T1();
+ gen_op_ljmp_protected_T0_T1(s->pc - s->cs_base);
} else {
gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
gen_op_movl_T0_T1();
val = insn_get(s, ot);
gen_op_movl_T1_im(val);
} else if (b == 0x6b) {
- val = insn_get(s, OT_BYTE);
+ val = (int8_t)insn_get(s, OT_BYTE);
gen_op_movl_T1_im(val);
} else {
gen_op_mov_TN_reg[ot][1][reg]();
case 0x8d: /* lea */
ot = dflag ? OT_LONG : OT_WORD;
modrm = ldub_code(s->pc++);
+ mod = (modrm >> 6) & 3;
+ if (mod == 3)
+ goto illegal_op;
reg = (modrm >> 3) & 7;
/* we must ensure that no segment is added */
s->override = -1;
/************************/
/* floats */
case 0xd8 ... 0xdf:
+ if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
+ /* if CR0.EM or CR0.TS are set, generate an FPU exception */
+ /* XXX: what to do if illegal op ? */
+ gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
+ break;
+ }
modrm = ldub_code(s->pc++);
mod = (modrm >> 6) & 3;
rm = modrm & 7;
op = ((b & 7) << 3) | ((modrm >> 3) & 7);
-
if (mod != 3) {
/* memory op */
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
case 0x0a: /* grp d9/2 */
switch(rm) {
case 0: /* fnop */
+ /* check exceptions (FreeBSD FPU probe) */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_fwait();
break;
default:
goto illegal_op;
gen_op_fcomi_ST0_FT0();
s->cc_op = CC_OP_EFLAGS;
break;
+ case 0x28: /* ffree sti */
+ gen_op_ffree_STN(opreg);
+ break;
case 0x2a: /* fst sti */
gen_op_fmov_STN_ST0(opreg);
break;
goto illegal_op;
}
}
+#ifdef USE_CODE_COPY
+ s->tb->cflags |= CF_TB_FP_USED;
+#endif
break;
/************************/
/* string ops */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_op_jmp_im(pc_start - s->cs_base);
- gen_op_iret_protected(s->dflag);
+ gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
s->cc_op = CC_OP_EFLAGS;
}
gen_eob(s);
modrm = ldub_code(s->pc++);
reg = (modrm >> 3) & 7;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+ /* NOTE: in order to handle the 0 case, we must load the
+ result. It could be optimized with a generated jump */
+ gen_op_mov_TN_reg[ot][1][reg]();
gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
- /* NOTE: we always write back the result. Intel doc says it is
- undefined if T0 == 0 */
- gen_op_mov_reg_T0[ot][reg]();
+ gen_op_mov_reg_T1[ot][reg]();
s->cc_op = CC_OP_LOGICB + ot;
break;
/************************/
/************************/
/* misc */
case 0x90: /* nop */
+ /* XXX: correct lock test for all insn */
+ if (prefixes & PREFIX_LOCK)
+ goto illegal_op;
break;
case 0x9b: /* fwait */
+ if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
+ (HF_MP_MASK | HF_TS_MASK)) {
+ gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
+ } else {
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_fwait();
+ }
break;
case 0xcc: /* int3 */
gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
mod = (modrm >> 6) & 3;
if (mod == 3)
goto illegal_op;
- gen_op_mov_reg_T0[ot][reg]();
+ gen_op_mov_TN_reg[ot][0][reg]();
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
if (ot == OT_WORD)
gen_op_boundw(pc_start - s->cs_base);
case 0x131: /* rdtsc */
gen_op_rdtsc();
break;
+ case 0x134: /* sysenter */
+ if (!s->pe) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if (s->cc_op != CC_OP_DYNAMIC) {
+ gen_op_set_cc_op(s->cc_op);
+ s->cc_op = CC_OP_DYNAMIC;
+ }
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_sysenter();
+ gen_eob(s);
+ }
+ break;
+ case 0x135: /* sysexit */
+ if (!s->pe) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if (s->cc_op != CC_OP_DYNAMIC) {
+ gen_op_set_cc_op(s->cc_op);
+ s->cc_op = CC_OP_DYNAMIC;
+ }
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_sysexit();
+ gen_eob(s);
+ }
+ break;
case 0x1a2: /* cpuid */
gen_op_cpuid();
break;
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
gen_op_clts();
+ /* abort block because static cpu state changed */
+ gen_op_jmp_im(s->pc - s->cs_base);
+ gen_eob(s);
}
break;
default:
gen_op_unlock();
return s->pc;
illegal_op:
+ if (s->prefix & PREFIX_LOCK)
+ gen_op_unlock();
/* XXX: ensure that no lock was generated */
gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
return s->pc;
[INDEX_op_cmc] = CC_C,
[INDEX_op_salc] = CC_C,
+ /* needed for correct flag optimisation before string ops */
+ [INDEX_op_jz_ecxw] = CC_OSZAPC,
+ [INDEX_op_jz_ecxl] = CC_OSZAPC,
+ [INDEX_op_jz_ecxw_im] = CC_OSZAPC,
+ [INDEX_op_jz_ecxl_im] = CC_OSZAPC,
+
#define DEF_READF(SUFFIX)\
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,
- DEF_READF()
+ DEF_READF( )
DEF_READF(_raw)
#ifndef CONFIG_USER_ONLY
DEF_READF(_kernel)
[INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,
- DEF_WRITEF()
+ DEF_WRITEF( )
DEF_WRITEF(_raw)
#ifndef CONFIG_USER_ONLY
DEF_WRITEF(_kernel)
[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,
- DEF_SIMPLER()
+ DEF_SIMPLER( )
DEF_SIMPLER(_raw)
#ifndef CONFIG_USER_ONLY
DEF_SIMPLER(_kernel)
DisasContext dc1, *dc = &dc1;
uint8_t *pc_ptr;
uint16_t *gen_opc_end;
- int flags, j, lj;
+ int flags, j, lj, cflags;
uint8_t *pc_start;
uint8_t *cs_base;
pc_start = (uint8_t *)tb->pc;
cs_base = (uint8_t *)tb->cs_base;
flags = tb->flags;
-
+ cflags = tb->cflags;
+
dc->pe = (flags >> HF_PE_SHIFT) & 1;
dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
else
dc->mem_index = 3;
}
+ dc->flags = flags;
dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
);
#if 0
/* check addseg logic */
- if (!dc->addseg && (dc->vm86 || !dc->pe))
+ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
printf("ERROR addseg\n");
#endif
the flag and abort the translation to give the irqs a
change to be happen */
if (dc->tf || dc->singlestep_enabled ||
- (flags & HF_INHIBIT_IRQ_MASK)) {
+ (flags & HF_INHIBIT_IRQ_MASK) ||
+ (cflags & CF_SINGLE_INSN)) {
gen_op_jmp_im(pc_ptr - dc->cs_base);
gen_eob(dc);
break;
}
#ifdef DEBUG_DISAS
- if (loglevel) {
+ if (loglevel & CPU_LOG_TB_CPU) {
+ cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
+ }
+ if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "----------------\n");
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
fprintf(logfile, "\n");
-#if 0
- fprintf(logfile, "OP:\n");
- dump_ops(gen_opc_buf, gen_opparam_buf);
- fprintf(logfile, "\n");
-#endif
+ if (loglevel & CPU_LOG_TB_OP) {
+ fprintf(logfile, "OP:\n");
+ dump_ops(gen_opc_buf, gen_opparam_buf);
+ fprintf(logfile, "\n");
+ }
}
#endif
optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
#ifdef DEBUG_DISAS
- if (loglevel) {
+ if (loglevel & CPU_LOG_TB_OP_OPT) {
fprintf(logfile, "AFTER FLAGS OPT:\n");
dump_ops(gen_opc_buf, gen_opparam_buf);
fprintf(logfile, "\n");
projects / qemu.git / blobdiff