*/
#include "cpu.h"
-#include "host-utils.h"
+#include "qemu/host-utils.h"
int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx)
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
{
- return addr & TARGET_PAGE_MASK;
+ addr &= TARGET_PAGE_MASK;
+ if (env->flags & LM32_FLAG_IGNORE_MSB) {
+ return addr & 0x7fffffff;
+ } else {
+ return addr;
+ }
}
-void do_interrupt(CPULM32State *env)
+void lm32_cpu_do_interrupt(CPUState *cs)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
+
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x type=%x\n", env->pc, env->exception_index);
return cfg;
}
-CPULM32State *cpu_lm32_init(const char *cpu_model)
+LM32CPU *cpu_lm32_init(const char *cpu_model)
{
LM32CPU *cpu;
CPULM32State *env;
const LM32Def *def;
- static int tcg_initialized;
def = cpu_lm32_find_by_name(cpu_model);
if (!def) {
env->num_bps = def->num_breakpoints;
env->num_wps = def->num_watchpoints;
env->cfg = cfg_by_def(def);
- env->flags = 0;
- cpu_exec_init(env);
- cpu_state_reset(env);
- qemu_init_vcpu(env);
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
- if (tcg_enabled() && !tcg_initialized) {
- tcg_initialized = 1;
- lm32_translate_init();
- }
-
- return env;
+ return cpu;
}
/* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
env->flags &= ~LM32_FLAG_IGNORE_MSB;
}
}
-
-void cpu_state_reset(CPULM32State *env)
-{
- if (qemu_loglevel_mask(CPU_LOG_RESET)) {
- qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
- log_cpu_state(env, 0);
- }
-
- tlb_flush(env, 1);
-
- /* reset cpu state */
- memset(env, 0, offsetof(CPULM32State, breakpoints));
-}
-