misc: move include files to include/qemu/

[qemu.git] / target-lm32 / helper.c

diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 9de777f43ec4df2dd2fdb9b5e824bca640731acc..d76ea3fe096a595da27aff0f447375a8355e0b6c 100644 (file)
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -18,7 +18,7 @@
  */
 
 #include "cpu.h"
-#include "host-utils.h"
+#include "qemu/host-utils.h"
 
 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
                               int mmu_idx)
@@ -37,7 +37,7 @@ int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
     return 0;
 }
 
-target_phys_addr_t cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
 {
     return addr & TARGET_PAGE_MASK;
 }
@@ -192,7 +192,7 @@ static uint32_t cfg_by_def(const LM32Def *def)
     return cfg;
 }
 
-CPULM32State *cpu_lm32_init(const char *cpu_model)
+LM32CPU *cpu_lm32_init(const char *cpu_model)
 {
     LM32CPU *cpu;
     CPULM32State *env;
@@ -219,7 +219,7 @@ CPULM32State *cpu_lm32_init(const char *cpu_model)
         lm32_translate_init();
     }
 
-    return env;
+    return cpu;
 }
 
 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
@@ -233,17 +233,3 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
         env->flags &= ~LM32_FLAG_IGNORE_MSB;
     }
 }
-
-void cpu_state_reset(CPULM32State *env)
-{
-    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
-        qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
-        log_cpu_state(env, 0);
-    }
-
-    tlb_flush(env, 1);
-
-    /* reset cpu state */
-    memset(env, 0, offsetof(CPULM32State, breakpoints));
-}
-