#define EXCP_HW_BREAK 5
#define EXCP_HW_EXCP 6
+/* MicroBlaze-specific interrupt pending bits. */
+#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
+
/* Register aliases. R0 - R15 */
#define R_SP 1
#define SR_PC 0
#define ESR_DIZ (1<<11) /* Zone Protection */
#define ESR_S (1<<10) /* Store instruction */
+#define ESR_ESS_FSL_OFFSET 5
+
#define ESR_EC_FSL 0
#define ESR_EC_UNALIGNED_DATA 1
#define ESR_EC_ILLEGAL_OP 2
#define ESR_EC_INSN_STORAGE 9
#define ESR_EC_DATA_TLB 10
#define ESR_EC_INSN_TLB 11
+#define ESR_EC_MASK 31
/* Floating Point Status Register (FSR) Bits */
#define FSR_IO (1<<4) /* Invalid operation */
#define CC_EQ 0
#define NB_MMU_MODES 3
+
+#define STREAM_EXCEPTION (1 << 0)
+#define STREAM_ATOMIC (1 << 1)
+#define STREAM_TEST (1 << 2)
+#define STREAM_CONTROL (1 << 3)
+#define STREAM_NONBLOCK (1 << 4)
+
typedef struct CPUMBState {
uint32_t debug;
uint32_t btaken;
}
#if !defined(CONFIG_USER_ONLY)
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
- int is_asi, int size);
+void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+ int is_write, int is_exec, int is_asi, int size);
#endif
+
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->sregs[SR_PC] = tb->pc;
+}
+
#endif