Fix mfc0 and dmtc0 instructions on MIPS64, by Aurelien Jarno.

[qemu.git] / target-mips / TODO

diff --git a/target-mips/TODO b/target-mips/TODO
index 9faa041b2cb97aa56d2ac80a378276081c46bc17..a5842ff27612bb6b6023b9dbb1c7f6e3267543b8 100644 (file)
--- a/target-mips/TODO
+++ b/target-mips/TODO
@@ -6,23 +6,28 @@ General
 - [ls][dw][lr] report broken (aligned) BadVAddr
 - Missing per-CPU instruction decoding, currently all implemented
   instructions are regarded as valid
-- pcnet32 does not work for little endian emulation on big endian host
-  (probably not mips specific, but observable for mips-malta)
-- CP1 enable/disable is checked at translation time, not at execution
-  time, so it will have delayed effect.
+- Applications running on top of a emulated Linux segfault sometimes
+  when the Qemu FPU emulation is disabled. Also gdb inside the emulated
+  system does not work. Both problems are caused by insufficient
+  handling of self-modifying code.
+- Floating point exception emulation is incomplete.
 
 MIPS64
 ------
 - No 64bit TLB support
-- no 64bit wide registers for FPU
+- 64bit FPU not fully implemented
 - 64bit mul/div handling broken
 
 "Generic" 4Kc system emulation
 ------------------------------
 - Doesn't correspond to any real hardware.
 
+PICA 61 system emulation
+------------------------
+- No framebuffer support yet.
+
 MALTA system emulation
 ----------------------
 - We fake firmware support instead of doing the real thing
 - Real firmware falls over when trying to init RAM, presumably due
-  to lacking I2C emulation.
+  to lacking system controller emulation.