helper_raise_exception_err(exception, 0);
}
-void helper_interrupt_restart (void)
-{
- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
- !(env->CP0_Status & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Status & (1 << CP0St_IE)) &&
- (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
- env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
- helper_raise_exception(EXCP_EXT_INTERRUPT);
- }
-}
-
#if !defined(CONFIG_USER_ONLY)
static void do_restore_state (void *pc_ptr)
{
{
uint32_t mask = 0x00C00300;
uint32_t old = env->CP0_Cause;
+ int i;
if (env->insn_flags & ISA_MIPS32R2)
mask |= 1 << CP0Ca_DC;
else
cpu_mips_start_count(env);
}
+
+ /* Set/reset software interrupts */
+ for (i = 0 ; i < 2 ; i++) {
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
+ cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
+ }
+ }
}
void helper_mtc0_ebase (target_ulong arg1)
{
/* vectored interrupts not implemented */
- /* Multi-CPU not implemented */
- env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
+ env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
void helper_mtc0_config0 (target_ulong arg1)
}
/* MIPS MT functions */
-target_ulong helper_dmt(target_ulong arg1)
+target_ulong helper_dmt(void)
{
// TODO
- arg1 = 0;
- // rt = arg1
-
- return arg1;
+ return 0;
}
-target_ulong helper_emt(target_ulong arg1)
+target_ulong helper_emt(void)
{
// TODO
- arg1 = 0;
- // rt = arg1
-
- return arg1;
+ return 0;
}
-target_ulong helper_dvpe(target_ulong arg1)
+target_ulong helper_dvpe(void)
{
// TODO
- arg1 = 0;
- // rt = arg1
-
- return arg1;
+ return 0;
}
-target_ulong helper_evpe(target_ulong arg1)
+target_ulong helper_evpe(void)
{
// TODO
- arg1 = 0;
- // rt = arg1
-
- return arg1;
+ return 0;
}
#endif /* !CONFIG_USER_ONLY */
// TODO: store to TC register
}
-target_ulong helper_yield(target_ulong arg1)
+target_ulong helper_yield(target_ulong arg)
{
+ target_long arg1 = arg;
+
if (arg1 < 0) {
/* No scheduling policy implemented. */
if (arg1 != -2) {
{
if (float64_is_signaling_nan(a) ||
float64_is_signaling_nan(b) ||
- (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
+ (sig && (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)))) {
float_raise(float_flag_invalid, status);
return 1;
- } else if (float64_is_nan(a) || float64_is_nan(b)) {
+ } else if (float64_is_quiet_nan(a) || float64_is_quiet_nan(b)) {
return 1;
} else {
return 0;
{
if (float32_is_signaling_nan(a) ||
float32_is_signaling_nan(b) ||
- (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
+ (sig && (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)))) {
float_raise(float_flag_invalid, status);
return 1;
- } else if (float32_is_nan(a) || float32_is_nan(b)) {
+ } else if (float32_is_quiet_nan(a) || float32_is_quiet_nan(b)) {
return 1;
} else {
return 0;