};
/* global register indices */
-static TCGv cpu_env, bcond, btarget, current_fpu;
+static TCGv cpu_env, bcond, btarget;
+static TCGv fpu_fpr32[32], fpu_fpr32h[32], fpu_fpr64[32], fpu_fcr0, fpu_fcr31;
#include "gen-icount.h"
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
+static const char *fregnames_64[] =
+ { "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
+ "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
+ "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
+ "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", };
+
+static const char *fregnames_h[] =
+ { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
+ "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
+ "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
+ "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
+
#ifdef MIPS_DEBUG_DISAS
#define MIPS_DEBUG(fmt, args...) \
do { \
/* Floating point register moves. */
static inline void gen_load_fpr32 (TCGv t, int reg)
{
- tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
+ tcg_gen_mov_i32(t, fpu_fpr32[reg]);
}
static inline void gen_store_fpr32 (TCGv t, int reg)
{
- tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
+ tcg_gen_mov_i32(fpu_fpr32[reg], t);
}
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
{
- if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_ld_i64(t, current_fpu, 8 * reg);
- } else {
- TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
+ if (ctx->hflags & MIPS_HFLAG_F64)
+ tcg_gen_mov_i64(t, fpu_fpr64[reg]);
+ else {
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);
- tcg_gen_extu_i32_i64(t, r_tmp1);
+ tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]);
tcg_gen_shli_i64(t, t, 32);
- tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX);
- tcg_gen_extu_i32_i64(r_tmp2, r_tmp1);
+ tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]);
tcg_gen_or_i64(t, t, r_tmp2);
- tcg_temp_free(r_tmp1);
tcg_temp_free(r_tmp2);
}
}
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg)
{
- if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_st_i64(t, current_fpu, 8 * reg);
- } else {
- TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
-
- tcg_gen_trunc_i64_i32(r_tmp, t);
- tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX);
+ if (ctx->hflags & MIPS_HFLAG_F64)
+ tcg_gen_mov_i64(fpu_fpr64[reg], t);
+ else {
+ tcg_gen_trunc_i64_i32(fpu_fpr32[reg & ~1], t);
tcg_gen_shri_i64(t, t, 32);
- tcg_gen_trunc_i64_i32(r_tmp, t);
- tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);
- tcg_temp_free(r_tmp);
+ tcg_gen_trunc_i64_i32(fpu_fpr32[reg | 1], t);
}
}
static inline void gen_load_fpr32h (TCGv t, int reg)
{
- tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
+ tcg_gen_mov_i32(t, fpu_fpr32h[reg]);
}
static inline void gen_store_fpr32h (TCGv t, int reg)
{
- tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
+ tcg_gen_mov_i32(fpu_fpr32h[reg], t);
}
static inline void get_fp_cond (TCGv t)
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
- tcg_gen_shri_i32(r_tmp2, r_tmp1, 24);
+ tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24);
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe);
- tcg_gen_shri_i32(r_tmp1, r_tmp1, 23);
+ tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23);
tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1);
tcg_gen_or_i32(t, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp1);
gen_load_gpr(t0, rd);
gen_load_gpr(t1, rs);
- tcg_gen_ld_i32(r_tmp, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
- tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
+ tcg_gen_andi_i32(r_tmp, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
tcg_temp_free(r_tmp);
gen_load_fpr32(fp0, fs);
gen_load_fpr32(fp1, fd);
- tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
- tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
+ tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
tcg_gen_mov_i32(fp1, fp0);
tcg_temp_free(fp0);
gen_load_fpr64(ctx, fp0, fs);
gen_load_fpr64(ctx, fp1, fd);
- tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
- tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
+ tcg_gen_andi_i32(r_tmp1, fpu_fcr31, ccbit);
tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
tcg_gen_mov_i64(fp1, fp0);
tcg_temp_free(fp0);
fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
- env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
- get_float_exception_flags(&env->fpu->fp_status));
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
+ get_float_exception_flags(&env->active_fpu.fp_status));
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
fpu_fprintf(f, "%3s: ", fregnames[i]);
- printfpr(&env->fpu->fpr[i]);
+ printfpr(&env->active_fpu.fpr[i]);
}
#undef printfpr
static void mips_tcg_init(void)
{
+ int i;
static int inited;
/* Initialize various static tables. */
offsetof(CPUState, bcond), "bcond");
btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, btarget), "btarget");
- current_fpu = tcg_global_mem_new(TCG_TYPE_PTR,
- TCG_AREG0,
- offsetof(CPUState, fpu),
- "current_fpu");
+ for (i = 0; i < 32; i++)
+ fpu_fpr32[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]),
+ fregnames[i]);
+ for (i = 0; i < 32; i++)
+ fpu_fpr64[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i]),
+ fregnames_64[i]);
+ for (i = 0; i < 32; i++)
+ fpu_fpr32h[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]),
+ fregnames_h[i]);
+ fpu_fcr0 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, active_fpu.fcr0),
+ "fcr0");
+ fpu_fcr31 = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, active_fpu.fcr31),
+ "fcr31");
/* register helpers */
#undef DEF_HELPER
projects / qemu.git / blobdiff