target-mips: get rid of tests on env->user_mode_only

[qemu.git] / target-mips / translate_init.c

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 57666d4db7800abe24fbaf7fdc8e8d36576105d6..d0243aa1d9d96a388a5ea2339ce2e97cadc71ceb 100644 (file)
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -16,7 +16,7 @@
  *
  * You should have received a copy of the GNU Lesser General Public
  * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  */
 
 /* CPU / CPU family specific config register values. */
@@ -63,7 +63,7 @@ enum mips_mmu_types {
 };
 
 struct mips_def_t {
-    const unsigned char *name;
+    const char *name;
     int32_t CP0_PRid;
     int32_t CP0_Config0;
     int32_t CP0_Config1;
@@ -95,7 +95,7 @@ struct mips_def_t {
 
 /*****************************************************************************/
 /* MIPS CPU definitions */
-static mips_def_t mips_defs[] =
+static const mips_def_t mips_defs[] =
 {
     {
         .name = "4Kc",
@@ -403,9 +403,9 @@ static mips_def_t mips_defs[] =
         .SYNCI_Step = 32,
         .CCRes = 2,
         .CP0_Status_rw_bitmask = 0x36FBFFFF,
-        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
-                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
-                    (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
+        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
+                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
         .SEGBITS = 42,
         /* The architectural limit is 59, but we have hardcoded 36 bit
            in some places...
@@ -417,11 +417,11 @@ static mips_def_t mips_defs[] =
 #endif
 };
 
-static const mips_def_t *cpu_mips_find_by_name (const unsigned char *name)
+static const mips_def_t *cpu_mips_find_by_name (const char *name)
 {
     int i;
 
-    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
+    for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
         if (strcasecmp(name, mips_defs[i].name) == 0) {
             return &mips_defs[i];
         }
@@ -433,7 +433,7 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 {
     int i;
 
-    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
+    for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
         (*cpu_fprintf)(f, "MIPS '%s'\n",
                        mips_defs[i].name);
     }
@@ -489,15 +489,20 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 
 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
+    int i;
+
+    for (i = 0; i < MIPS_FPU_MAX; i++)
+        env->fpus[i].fcr0 = def->CP1_fcr0;
 
-    env->fpu->fcr0 = def->CP1_fcr0;
-#ifdef CONFIG_USER_ONLY
+    memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
+#if defined(CONFIG_USER_ONLY)
     if (env->CP0_Config1 & (1 << CP0C1_FP))
         env->hflags |= MIPS_HFLAG_FPU;
-    if (env->fpu->fcr0 & (1 << FCR0_F64))
+#ifdef TARGET_MIPS64
+    if (env->active_fpu.fcr0 & (1 << FCR0_F64))
         env->hflags |= MIPS_HFLAG_F64;
 #endif
+#endif
 }
 
 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
@@ -510,15 +515,16 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
        implemented, 5 TCs implemented. */
     env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-#ifndef CONFIG_USER_ONLY
-                             /* Usermode has no TLB support */
-                             (env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
-#endif
 // TODO: actually do 2 VPEs.
 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 //                             (0x04 << CP0MVPC0_PTC);
                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
                              (0x04 << CP0MVPC0_PTC);
+#if !defined(CONFIG_USER_ONLY)
+    /* Usermode has no TLB support */
+    env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+#endif
+
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
     env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
@@ -543,6 +549,7 @@ static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
     env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
     env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
     env->CP0_SRSCtl = def->CP0_SRSCtl;
+    env->current_tc = 0;
     env->SEGBITS = def->SEGBITS;
     env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1);
 #if defined(TARGET_MIPS64)