* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/* A lot of PowerPC definition have been included here.
*/
#include "dis-asm.h"
-#include "host-utils.h"
+#include "gdbstub.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
#endif
struct ppc_def_t {
- const unsigned char *name;
+ const char *name;
uint32_t pvr;
uint32_t svr;
uint64_t insns_flags;
+ uint64_t insns_flags2;
uint64_t msr_mask;
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
PPC_IRQ_INIT_FN(40x);
PPC_IRQ_INIT_FN(6xx);
PPC_IRQ_INIT_FN(970);
+PPC_IRQ_INIT_FN(POWER7);
+PPC_IRQ_INIT_FN(e500);
/* Generic callbacks:
* do nothing but store/retrieve spr value
*/
-#ifdef PPC_DUMP_SPR_ACCESSES
-static void spr_read_generic (void *opaque, int sprn)
-{
- gen_op_load_dump_spr(sprn);
-}
-
-static void spr_write_generic (void *opaque, int sprn)
+static void spr_read_generic (void *opaque, int gprn, int sprn)
{
- gen_op_store_dump_spr(sprn);
-}
-#else
-static void spr_read_generic (void *opaque, int sprn)
-{
- gen_op_load_spr(sprn);
+ gen_load_spr(cpu_gpr[gprn], sprn);
+#ifdef PPC_DUMP_SPR_ACCESSES
+ {
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_load_dump_spr(t0);
+ tcg_temp_free_i32(t0);
+ }
+#endif
}
-static void spr_write_generic (void *opaque, int sprn)
+static void spr_write_generic (void *opaque, int sprn, int gprn)
{
- gen_op_store_spr(sprn);
-}
+ gen_store_spr(sprn, cpu_gpr[gprn]);
+#ifdef PPC_DUMP_SPR_ACCESSES
+ {
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_store_dump_spr(t0);
+ tcg_temp_free_i32(t0);
+ }
#endif
+}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_clear (void *opaque, int sprn)
+static void spr_write_clear (void *opaque, int sprn, int gprn)
{
- gen_op_mask_spr(sprn);
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ gen_load_spr(t0, sprn);
+ tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
+ tcg_gen_and_tl(t0, t0, t1);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
}
#endif
/* SPR common to all PowerPC */
/* XER */
-static void spr_read_xer (void *opaque, int sprn)
+static void spr_read_xer (void *opaque, int gprn, int sprn)
{
- gen_op_load_xer();
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
}
-static void spr_write_xer (void *opaque, int sprn)
+static void spr_write_xer (void *opaque, int sprn, int gprn)
{
- gen_op_store_xer();
+ tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
}
/* LR */
-static void spr_read_lr (void *opaque, int sprn)
+static void spr_read_lr (void *opaque, int gprn, int sprn)
{
- gen_op_load_lr();
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
}
-static void spr_write_lr (void *opaque, int sprn)
+static void spr_write_lr (void *opaque, int sprn, int gprn)
{
- gen_op_store_lr();
+ tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
}
/* CTR */
-static void spr_read_ctr (void *opaque, int sprn)
+static void spr_read_ctr (void *opaque, int gprn, int sprn)
{
- gen_op_load_ctr();
+ tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
}
-static void spr_write_ctr (void *opaque, int sprn)
+static void spr_write_ctr (void *opaque, int sprn, int gprn)
{
- gen_op_store_ctr();
+ tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
}
/* User read access to SPR */
/* UPMCx */
/* USIA */
/* UDECR */
-static void spr_read_ureg (void *opaque, int sprn)
+static void spr_read_ureg (void *opaque, int gprn, int sprn)
{
- gen_op_load_spr(sprn + 0x10);
+ gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
}
/* SPR common to all non-embedded PowerPC */
/* DECR */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_decr (void *opaque, int sprn)
+static void spr_read_decr (void *opaque, int gprn, int sprn)
{
- gen_op_load_decr();
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_load_decr(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
}
-static void spr_write_decr (void *opaque, int sprn)
+static void spr_write_decr (void *opaque, int sprn, int gprn)
{
- gen_op_store_decr();
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_store_decr(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
}
#endif
/* SPR common to all non-embedded PowerPC, except 601 */
/* Time base */
-static void spr_read_tbl (void *opaque, int sprn)
+static void spr_read_tbl (void *opaque, int gprn, int sprn)
{
- gen_op_load_tbl();
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_load_tbl(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
}
-static void spr_read_tbu (void *opaque, int sprn)
+static void spr_read_tbu (void *opaque, int gprn, int sprn)
{
- gen_op_load_tbu();
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_load_tbu(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
}
__attribute__ (( unused ))
-static void spr_read_atbl (void *opaque, int sprn)
+static void spr_read_atbl (void *opaque, int gprn, int sprn)
{
- gen_op_load_atbl();
+ gen_helper_load_atbl(cpu_gpr[gprn]);
}
__attribute__ (( unused ))
-static void spr_read_atbu (void *opaque, int sprn)
+static void spr_read_atbu (void *opaque, int gprn, int sprn)
{
- gen_op_load_atbu();
+ gen_helper_load_atbu(cpu_gpr[gprn]);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_tbl (void *opaque, int sprn)
+static void spr_write_tbl (void *opaque, int sprn, int gprn)
{
- gen_op_store_tbl();
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_store_tbl(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
+}
+
+static void spr_write_tbu (void *opaque, int sprn, int gprn)
+{
+ if (use_icount) {
+ gen_io_start();
+ }
+ gen_helper_store_tbu(cpu_gpr[gprn]);
+ if (use_icount) {
+ gen_io_end();
+ gen_stop_exception(opaque);
+ }
}
-static void spr_write_tbu (void *opaque, int sprn)
+__attribute__ (( unused ))
+static void spr_write_atbl (void *opaque, int sprn, int gprn)
{
- gen_op_store_tbu();
+ gen_helper_store_atbl(cpu_gpr[gprn]);
}
__attribute__ (( unused ))
-static void spr_write_atbl (void *opaque, int sprn)
+static void spr_write_atbu (void *opaque, int sprn, int gprn)
{
- gen_op_store_atbl();
+ gen_helper_store_atbu(cpu_gpr[gprn]);
}
+#if defined(TARGET_PPC64)
__attribute__ (( unused ))
-static void spr_write_atbu (void *opaque, int sprn)
+static void spr_read_purr (void *opaque, int gprn, int sprn)
{
- gen_op_store_atbu();
+ gen_helper_load_purr(cpu_gpr[gprn]);
}
#endif
+#endif
#if !defined(CONFIG_USER_ONLY)
/* IBAT0U...IBAT0U */
/* IBAT0L...IBAT7L */
-static void spr_read_ibat (void *opaque, int sprn)
+static void spr_read_ibat (void *opaque, int gprn, int sprn)
{
- gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_read_ibat_h (void *opaque, int sprn)
+static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
{
- gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
}
-static void spr_write_ibatu (void *opaque, int sprn)
+static void spr_write_ibatu (void *opaque, int sprn, int gprn)
{
- gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_ibatu_h (void *opaque, int sprn)
+static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
{
- gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl (void *opaque, int sprn)
+static void spr_write_ibatl (void *opaque, int sprn, int gprn)
{
- gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_ibatl_h (void *opaque, int sprn)
+static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
{
- gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
/* DBAT0U...DBAT7U */
/* DBAT0L...DBAT7L */
-static void spr_read_dbat (void *opaque, int sprn)
+static void spr_read_dbat (void *opaque, int gprn, int sprn)
{
- gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
}
-static void spr_read_dbat_h (void *opaque, int sprn)
+static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
{
- gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
}
-static void spr_write_dbatu (void *opaque, int sprn)
+static void spr_write_dbatu (void *opaque, int sprn, int gprn)
{
- gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_dbatu_h (void *opaque, int sprn)
+static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
{
- gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl (void *opaque, int sprn)
+static void spr_write_dbatl (void *opaque, int sprn, int gprn)
{
- gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_dbatl_h (void *opaque, int sprn)
+static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
{
- gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
+ TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
/* SDR1 */
-static void spr_read_sdr1 (void *opaque, int sprn)
-{
- gen_op_load_sdr1();
-}
-
-static void spr_write_sdr1 (void *opaque, int sprn)
+static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
{
- gen_op_store_sdr1();
+ gen_helper_store_sdr1(cpu_gpr[gprn]);
}
/* 64 bits PowerPC specific SPRs */
/* ASR */
#if defined(TARGET_PPC64)
-__attribute__ (( unused ))
-static void spr_read_asr (void *opaque, int sprn)
+static void spr_read_hior (void *opaque, int gprn, int sprn)
{
- gen_op_load_asr();
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
}
-__attribute__ (( unused ))
-static void spr_write_asr (void *opaque, int sprn)
+static void spr_write_hior (void *opaque, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
+ tcg_temp_free(t0);
+}
+
+static void spr_read_asr (void *opaque, int gprn, int sprn)
+{
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
+}
+
+static void spr_write_asr (void *opaque, int sprn, int gprn)
{
- gen_op_store_asr();
+ gen_helper_store_asr(cpu_gpr[gprn]);
}
#endif
#endif
/* PowerPC 601 specific registers */
/* RTC */
-static void spr_read_601_rtcl (void *opaque, int sprn)
+static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
{
- gen_op_load_601_rtcl();
+ gen_helper_load_601_rtcl(cpu_gpr[gprn]);
}
-static void spr_read_601_rtcu (void *opaque, int sprn)
+static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
{
- gen_op_load_601_rtcu();
+ gen_helper_load_601_rtcu(cpu_gpr[gprn]);
}
#if !defined(CONFIG_USER_ONLY)
-static void spr_write_601_rtcu (void *opaque, int sprn)
+static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
{
- gen_op_store_601_rtcu();
+ gen_helper_store_601_rtcu(cpu_gpr[gprn]);
}
-static void spr_write_601_rtcl (void *opaque, int sprn)
+static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
{
- gen_op_store_601_rtcl();
+ gen_helper_store_601_rtcl(cpu_gpr[gprn]);
}
-static void spr_write_hid0_601 (void *opaque, int sprn)
+static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
{
DisasContext *ctx = opaque;
- gen_op_store_hid0_601();
+ gen_helper_store_hid0_601(cpu_gpr[gprn]);
/* Must stop the translation as endianness may have changed */
- GEN_STOP(ctx);
+ gen_stop_exception(ctx);
}
#endif
/* Unified bats */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_601_ubat (void *opaque, int sprn)
+static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
{
- gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
}
-static void spr_write_601_ubatu (void *opaque, int sprn)
+static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
{
- gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_601_ubatl (void *opaque, int sprn)
+static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
{
- gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
+ TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
#endif
/* PowerPC 40x specific registers */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_40x_pit (void *opaque, int sprn)
+static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
{
- gen_op_load_40x_pit();
+ gen_helper_load_40x_pit(cpu_gpr[gprn]);
}
-static void spr_write_40x_pit (void *opaque, int sprn)
+static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
{
- gen_op_store_40x_pit();
+ gen_helper_store_40x_pit(cpu_gpr[gprn]);
}
-static void spr_write_40x_dbcr0 (void *opaque, int sprn)
+static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
{
DisasContext *ctx = opaque;
- gen_op_store_40x_dbcr0();
+ gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
- GEN_STOP(ctx);
+ gen_stop_exception(ctx);
}
-static void spr_write_40x_sler (void *opaque, int sprn)
+static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
{
- gen_op_store_40x_sler();
+ gen_helper_store_40x_sler(cpu_gpr[gprn]);
}
-static void spr_write_booke_tcr (void *opaque, int sprn)
+static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
{
- gen_op_store_booke_tcr();
+ gen_helper_store_booke_tcr(cpu_gpr[gprn]);
}
-static void spr_write_booke_tsr (void *opaque, int sprn)
+static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
{
- gen_op_store_booke_tsr();
+ gen_helper_store_booke_tsr(cpu_gpr[gprn]);
}
#endif
/* PowerPC 403 specific registers */
/* PBL1 / PBU1 / PBL2 / PBU2 */
#if !defined(CONFIG_USER_ONLY)
-static void spr_read_403_pbr (void *opaque, int sprn)
+static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
{
- gen_op_load_403_pb(sprn - SPR_403_PBL1);
+ tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
}
-static void spr_write_403_pbr (void *opaque, int sprn)
+static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
{
- gen_op_store_403_pb(sprn - SPR_403_PBL1);
+ TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
+ gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
}
-static void spr_write_pir (void *opaque, int sprn)
+static void spr_write_pir (void *opaque, int sprn, int gprn)
{
- gen_op_store_pir();
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
+ gen_store_spr(SPR_PIR, t0);
+ tcg_temp_free(t0);
}
#endif
+/* SPE specific registers */
+static void spr_read_spefscr (void *opaque, int gprn, int sprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
+ tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_spefscr (void *opaque, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
+ tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
+ tcg_temp_free_i32(t0);
+}
+
#if !defined(CONFIG_USER_ONLY)
/* Callback used to write the exception vector base */
-static void spr_write_excp_prefix (void *opaque, int sprn)
+static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
{
- gen_op_store_excp_prefix();
- gen_op_store_spr(sprn);
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
}
-static void spr_write_excp_vector (void *opaque, int sprn)
+static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
{
DisasContext *ctx = opaque;
if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
- gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
- gen_op_store_spr(sprn);
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
} else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
- gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
- gen_op_store_spr(sprn);
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
+ tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
} else {
printf("Trying to write an unknown exception vector %d %03x\n",
sprn, sprn);
- GEN_EXCP_PRIVREG(ctx);
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
}
#endif
+static inline void vscr_init (CPUPPCState *env, uint32_t val)
+{
+ env->vscr = val;
+ /* Altivec always uses round-to-nearest */
+ set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
+ set_flush_to_zero(vscr_nj, &env->vec_status);
+}
+
#if defined(CONFIG_USER_ONLY)
#define spr_register(env, num, name, uea_read, uea_write, \
oea_read, oea_write, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, initial_value); \
} while (0)
static inline void _spr_register (CPUPPCState *env, int num,
- const unsigned char *name,
- void (*uea_read)(void *opaque, int sprn),
- void (*uea_write)(void *opaque, int sprn),
+ const char *name,
+ void (*uea_read)(void *opaque, int gprn, int sprn),
+ void (*uea_write)(void *opaque, int sprn, int gprn),
target_ulong initial_value)
#else
static inline void spr_register (CPUPPCState *env, int num,
- const unsigned char *name,
- void (*uea_read)(void *opaque, int sprn),
- void (*uea_write)(void *opaque, int sprn),
- void (*oea_read)(void *opaque, int sprn),
- void (*oea_write)(void *opaque, int sprn),
+ const char *name,
+ void (*uea_read)(void *opaque, int gprn, int sprn),
+ void (*uea_write)(void *opaque, int sprn, int gprn),
+ void (*oea_read)(void *opaque, int gprn, int sprn),
+ void (*oea_write)(void *opaque, int sprn, int gprn),
target_ulong initial_value)
#endif
{
exit(1);
}
#if defined(PPC_DEBUG_SPR)
- printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
- initial_value);
+ printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
+ name, initial_value);
#endif
spr->name = name;
spr->uea_read = uea_read;
/* Memory management */
spr_register(env, SPR_SDR1, "SDR1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_sdr1, &spr_write_sdr1,
+ &spr_read_generic, &spr_write_sdr1,
0x00000000);
}
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBL, "TBL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbl,
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
0x00000000);
spr_register(env, SPR_VTBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBU, "TBU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu,
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
0x00000000);
}
env->nb_tlb = nb_tlbs;
env->nb_ways = nb_ways;
env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
spr_register(env, SPR_DMISS, "DMISS",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* External access control */
- /* XXX : not implemented */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
}
/* SPR common to all 7xx PowerPC implementations */
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Performance monitors */
/* XXX : not implemented */
spr_register(env, SPR_MMCR0, "MMCR0",
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_MSSCR0, "MSSCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Not strictly an SPR */
+ vscr_init(env, 0x00010000);
}
static void gen_l3_ctrl (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* L3ITCR1 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR1, "L3ITCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR2 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR2, "L3ITCR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3ITCR3 */
- /* XXX : not implemented */
- spr_register(env, SPR_L3ITCR3, "L3ITCR3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* L3OHCR */
- /* XXX : not implemented */
- spr_register(env, SPR_L3OHCR, "L3OHCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* L3PM */
/* XXX : not implemented */
spr_register(env, SPR_L3PM, "L3PM",
env->nb_tlb = nb_tlbs;
env->nb_ways = nb_ways;
env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
/* XXX : not implemented */
spr_register(env, SPR_PTEHI, "PTEHI",
SPR_NOACCESS, SPR_NOACCESS,
#endif
}
+#if !defined(CONFIG_USER_ONLY)
+static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+}
+
+static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_booke206_tlbflush(t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
+{
+ TCGv_i32 t0 = tcg_const_i32(sprn);
+ gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
+ tcg_temp_free_i32(t0);
+}
+#endif
+
static void gen_spr_usprgh (CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
/* PowerPC BookE SPR */
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
{
- const unsigned char *ivor_names[64] = {
+ const char *ivor_names[64] = {
"IVOR0", "IVOR1", "IVOR2", "IVOR3",
"IVOR4", "IVOR5", "IVOR6", "IVOR7",
"IVOR8", "IVOR9", "IVOR10", "IVOR11",
}
spr_register(env, SPR_BOOKE_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
spr_register(env, SPR_BOOKE_TCR, "TCR",
SPR_NOACCESS, SPR_NOACCESS,
0x00000000);
}
-/* FSL storage control registers */
-static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
+static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
+ uint32_t maxsize, uint32_t flags,
+ uint32_t nentries)
+{
+ return (assoc << TLBnCFG_ASSOC_SHIFT) |
+ (minsize << TLBnCFG_MINSIZE_SHIFT) |
+ (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
+ flags | nentries;
+}
+
+/* BookE 2.06 storage control registers */
+static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
+ uint32_t *tlbncfg)
{
#if !defined(CONFIG_USER_ONLY)
- const unsigned char *mas_names[8] = {
+ const char *mas_names[8] = {
"MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
};
int mas_sprn[8] = {
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID1, "PID1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
if (env->nb_pids > 2) {
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID2, "PID2",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
/* XXX : not implemented */
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000); /* TOFIX */
- /* XXX : not implemented */
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000); /* TOFIX */
switch (env->nb_ways) {
case 4:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[3]);
/* Fallthru */
case 3:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[2]);
/* Fallthru */
case 2:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[1]);
/* Fallthru */
case 1:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[0]);
/* Fallthru */
case 0:
default:
break;
}
#endif
+
+ gen_spr_usprgh(env);
}
/* SPR specific to PowerPC 440 implementation */
/* SPR specific to PowerPC 620 */
static void gen_spr_620 (CPUPPCState *env)
{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+ spr_register(env, SPR_ASR, "ASR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_asr, &spr_write_asr,
+ 0x00000000);
+ /* Breakpoints */
+ /* XXX : not implemented */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_SDA, "SDA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_PMC1R, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_PMC1W, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_PMC2R, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_PMC2W, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_MMCR0R, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_620_MMCR0W, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if 0 // XXX: check this
/* XXX : not implemented */
spr_register(env, SPR_620_PMR0, "PMR0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+#endif
+ /* XXX : not implemented */
+ spr_register(env, SPR_620_BUSCSR, "BUSCSR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_620_HID8, "HID8",
+ spr_register(env, SPR_620_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_620_HID9, "HID9",
+ spr_register(env, SPR_620_L2SR, "L2SR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
* HSRR1 => SPR 315 (Power 2.04 hypv)
* LPCR => SPR 316 (970)
* LPIDR => SPR 317 (970)
- * SPEFSCR => SPR 512 (Power 2.04 emb)
* EPR => SPR 702 (Power 2.04 emb)
* perf => 768-783 (Power 2.04)
* perf => 784-799 (Power 2.04)
env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFF0UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFF0UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFF0UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFF0UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFF7UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
env->ivor_mask = 0x0000FFE0UL;
env->ivpr_mask = 0xFFFF0000UL;
/* Hardware reset vector */
env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
- env->excp_prefix = 0xFFF00000UL;
+ env->hreset_excp_prefix = 0xFFF00000UL;
/* Hardware reset vector */
env->hreset_vector = 0x00000100UL;
#endif
static void init_excp_602 (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
+ /* XXX: exception prefix has a special behavior on 602 */
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
- env->excp_prefix = 0xFFF00000UL;
+ env->hreset_excp_prefix = 0xFFF00000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0xFFF00000UL;
/* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
+ env->hreset_vector = 0x00000100UL;
#endif
}
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
- env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
- env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
- env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0xFFF00000UL;
+ env->hreset_excp_prefix = 0xFFF00000UL;
/* Hardware reset vector */
env->hreset_vector = 0x0000000000000100ULL;
#endif
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
}
-static void init_excp_750FX (CPUPPCState *env)
+static void init_excp_750cl (CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
+ env->hreset_excp_prefix = 0x00000000UL;
+ /* Hardware reset vector */
+ env->hreset_vector = 0xFFFFFFFCUL;
+#endif
+}
+
+static void init_excp_750cx (CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
- env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
- env->excp_prefix = 0x00000000UL;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
- env->excp_prefix = 0x00000000UL;
+ env->hreset_excp_prefix = 0x00000000UL;
/* Hardware reset vector */
env->hreset_vector = 0xFFFFFFFCUL;
#endif
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
- env->excp_prefix = 0x00000000FFF00000ULL;
+ env->hreset_excp_prefix = 0x00000000FFF00000ULL;
/* Hardware reset vector */
env->hreset_vector = 0x0000000000000100ULL;
#endif
}
-#endif
-
-/*****************************************************************************/
-/* Power management enable checks */
-static int check_pow_none (CPUPPCState *env)
-{
- return 0;
-}
-
-static int check_pow_nocheck (CPUPPCState *env)
-{
- return 1;
-}
-static int check_pow_hid0 (CPUPPCState *env)
+static void init_excp_POWER7 (CPUPPCState *env)
{
- if (env->spr[SPR_HID0] & 0x00E00000)
- return 1;
-
- return 0;
-}
-
-/*****************************************************************************/
-/* PowerPC implementations definitions */
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
+ env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
+ env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
+ env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
+ env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
+ env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
+ env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
+ env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
+ env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
+ env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
+ env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
+ env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
+ env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
+ env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
+ env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
+ env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
+ env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
+ env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
+ env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
+ env->hreset_excp_prefix = 0;
+ /* Hardware reset vector */
+ env->hreset_vector = 0x0000000000000100ULL;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/* Power management enable checks */
+static int check_pow_none (CPUPPCState *env)
+{
+ return 0;
+}
+
+static int check_pow_nocheck (CPUPPCState *env)
+{
+ return 1;
+}
+
+static int check_pow_hid0 (CPUPPCState *env)
+{
+ if (env->spr[SPR_HID0] & 0x00E00000)
+ return 1;
+
+ return 0;
+}
+
+static int check_pow_hid0_74xx (CPUPPCState *env)
+{
+ if (env->spr[SPR_HID0] & 0x00600000)
+ return 1;
+
+ return 0;
+}
-/* PowerPC 40x instruction set */
-#define POWERPC_INSNS_EMB (PPC_INSNS_BASE | PPC_WRTEE | \
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ)
+/*****************************************************************************/
+/* PowerPC implementations definitions */
/* PowerPC 401 */
-#define POWERPC_INSNS_401 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_WRTEE | PPC_DCR | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_401 (PPC_NONE)
#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
}
/* PowerPC 401x2 */
-#define POWERPC_INSNS_401x2 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | PPC_MFTB | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_401x2 (PPC_NONE)
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
}
/* PowerPC 401x3 */
-#define POWERPC_INSNS_401x3 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | PPC_MFTB | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_401x3 (PPC_NONE)
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
}
/* IOP480 */
-#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_CACHE_DCBA | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_IOP480 (PPC_NONE)
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
}
/* PowerPC 403 */
-#define POWERPC_INSNS_403 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_403 (PPC_NONE)
#define POWERPC_MSRM_403 (0x000000000007D00DULL)
#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
ppc40x_irq_init(env);
-#if !defined(CONFIG_USER_ONLY)
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
}
/* PowerPC 403 GCX */
-#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
+#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
+ PPC_4xx_COMMON | PPC_40x_EXCP)
+#define POWERPC_INSNS2_403GCX (PPC_NONE)
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
}
/* PowerPC 405 */
-#define POWERPC_INSNS_405 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
- PPC_MFTB | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
+#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
- PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT | \
- PPC_405_MAC)
+ PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
+#define POWERPC_INSNS2_405 (PPC_NONE)
#define POWERPC_MSRM_405 (0x000000000006E630ULL)
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_4xx_softmmu(env);
env->dcache_line_size = 32;
}
/* PowerPC 440 EP */
-#define POWERPC_INSNS_440EP (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC | PPC_RFMCI)
+ PPC_440_SPEC)
+#define POWERPC_INSNS2_440EP (PPC_NONE)
#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
}
/* PowerPC 440 GP */
-#define POWERPC_INSNS_440GP (POWERPC_INSNS_EMB | PPC_STRING | \
- PPC_DCR | PPC_DCRX | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
- PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
+#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
+#define POWERPC_INSNS2_440GP (PPC_NONE)
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
}
/* PowerPC 440x4 */
-#define POWERPC_INSNS_440x4 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+#define POWERPC_INSNS2_440x4 (PPC_NONE)
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
}
/* PowerPC 440x5 */
-#define POWERPC_INSNS_440x5 (POWERPC_INSNS_EMB | PPC_STRING | PPC_DCR | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
+#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
- PPC_440_SPEC | PPC_RFMCI)
+ PPC_440_SPEC)
+#define POWERPC_INSNS2_440x5 (PPC_NONE)
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
#define check_pow_440x5 check_pow_nocheck
-__attribute__ (( unused ))
static void init_proc_440x5 (CPUPPCState *env)
{
/* Time base */
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
+ ppc40x_irq_init(env);
}
/* PowerPC 460 (guessed) */
-#define POWERPC_INSNS_460 (POWERPC_INSNS_EMB | PPC_STRING | \
+#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
PPC_DCR | PPC_DCRX | PPC_DCRUX | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
- PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
+ PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
+#define POWERPC_INSNS2_460 (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
}
/* PowerPC 460F (guessed) */
-#define POWERPC_INSNS_460F (POWERPC_INSNS_EMB | PPC_STRING | \
+#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
+ PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | PPC_MFTB | \
PPC_DCR | PPC_DCRX | PPC_DCRUX | \
- PPC_CACHE_DCBA | PPC_MEM_TLBSYNC | \
- PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES | \
- PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
- PPC_FLOAT_STFIWX | \
- PPC_BOOKE | PPC_MFAPIDI | PPC_TLBIVA | \
- PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
+ PPC_WRTEE | PPC_MFAPIDI | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVA | \
+ PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
+ PPC_440_SPEC)
+#define POWERPC_INSNS2_460F (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_BookE(env);
env->dcache_line_size = 32;
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
PPC_MFTB)
+#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
PPC_CACHE_ICBI | PPC_MFTB)
+#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
/* Freescale 82xx cores (aka PowerQUICC-II) */
/* PowerPC G2 */
-#define POWERPC_INSNS_G2 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_G2 (PPC_NONE)
#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
gen_spr_G2(env);
/* Time base */
gen_tbl(env);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Hardware implementation register */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
}
/* PowerPC G2LE */
-#define POWERPC_INSNS_G2LE (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_G2LE (PPC_NONE)
#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
gen_spr_G2(env);
/* Time base */
gen_tbl(env);
+ /* External access control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Hardware implementation register */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
* tlbivax
* all SPE multiply-accumulate instructions
*/
-#define POWERPC_INSNS_e200 (POWERPC_INSNS_EMB | PPC_ISEL | \
- PPC_SPE | PPC_SPEFPU | \
+#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
+ PPC_SPE | PPC_SPE_SINGLE | \
+ PPC_WRTEE | PPC_RFDI | \
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
- PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
- PPC_BOOKE | PPC_RFDI)
+ PPC_BOOKE)
+#define POWERPC_INSNS2_e200 (PPC_NONE)
#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
-#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
+#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
gen_spr_BookE(env, 0x000000070000FFFFULL);
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_spefscr, &spr_write_spefscr,
+ &spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
- gen_spr_BookE_FSL(env, 0x0000005D);
+ gen_spr_BookE206(env, 0x0000005D, NULL);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000); /* TOFIX */
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
env->nb_tlb = 64;
env->nb_ways = 1;
env->id_tlbs = 0;
+ env->tlb_type = TLB_EMB;
#endif
init_excp_e200(env);
env->dcache_line_size = 32;
}
/* e300 core */
-#define POWERPC_INSNS_e300 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_e300 (PPC_NONE)
#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
gen_low_BATs(env);
+ gen_high_BATs(env);
gen_6xx_7xx_soft_tlb(env, 64, 2);
init_excp_603(env);
env->dcache_line_size = 32;
ppc6xx_irq_init(env);
}
-/* e500 core */
-#define POWERPC_INSNS_e500 (POWERPC_INSNS_EMB | PPC_ISEL | \
- PPC_SPE | PPC_SPEFPU | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
- PPC_CACHE_DCBA | PPC_CACHE_LOCK | \
- PPC_BOOKE | PPC_RFDI)
-#define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
-#define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
-#define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
-#define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
-#define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
-#define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
- POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
- POWERPC_FLAG_BUS_CLK)
-#define check_pow_e500 check_pow_hid0
+/* e500v1 core */
+#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
+ PPC_SPE | PPC_SPE_SINGLE | \
+ PPC_WRTEE | PPC_RFDI | \
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX)
+#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
+#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
+#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
+#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
+#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
+#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
+#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_e500v1 check_pow_hid0
+#define init_proc_e500v1 init_proc_e500v1
+
+/* e500v2 core */
+#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
+ PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
+ PPC_WRTEE | PPC_RFDI | \
+ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX)
+#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
+#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
+#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
+#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
+#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
+#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
+#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
+ POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_e500v2 check_pow_hid0
+#define init_proc_e500v2 init_proc_e500v2
+
+static void init_proc_e500 (CPUPPCState *env, int version)
+{
+ uint32_t tlbncfg[2];
+#if !defined(CONFIG_USER_ONLY)
+ int i;
+#endif
-__attribute__ (( unused ))
-static void init_proc_e500 (CPUPPCState *env)
-{
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ /*
+ * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
+ * complain when accessing them.
+ * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ */
+ gen_spr_BookE(env, 0x0000000F0000FFFFULL);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_spefscr, &spr_write_spefscr,
+ &spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_pids = 3;
+ env->nb_ways = 2;
+ env->id_tlbs = 0;
+ switch (version) {
+ case 1:
+ /* e500v1 */
+ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ case 2:
+ /* e500v2 */
+ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ default:
+ cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
+ }
#endif
- gen_spr_BookE_FSL(env, 0x0000005F);
+ gen_spr_BookE206(env, 0x000000DF, tlbncfg);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_e500_l1csr0,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke206_mmucsr0,
+ 0x00000000);
+
#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
+ env->nb_tlb = 0;
+ env->tlb_type = TLB_MAS;
+ for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+ env->nb_tlb += booke206_tlb_size(env, i);
+ }
#endif
+
init_excp_e200(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
+ /* Allocate hardware IRQ controller */
+ ppce500_irq_init(env);
+}
+
+static void init_proc_e500v1(CPUPPCState *env)
+{
+ init_proc_e500(env, 1);
+}
+
+static void init_proc_e500v2(CPUPPCState *env)
+{
+ init_proc_e500(env, 2);
}
/* Non-embedded PowerPC */
-/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */
-#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE)
-/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */
-#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \
- PPC_SEGMENT)
/* POWER : same as 601, without mfmsr, mfsr */
#if defined(TODO)
#endif /* TODO */
/* PowerPC 601 */
-#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \
- PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
+#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
+ PPC_FLOAT | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_601 (PPC_NONE)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
+#define POWERPC_MSRR_601 (0x0000000000001040ULL)
//#define POWERPC_MMU_601 (POWERPC_MMU_601)
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_601_HID15, "HID15",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 2;
- env->id_tlbs = 0;
-#endif
init_excp_601(env);
- env->dcache_line_size = 64;
+ /* XXX: beware that dcache line size is 64
+ * but dcbz uses 32 bytes "sectors"
+ * XXX: this breaks clcs instruction !
+ */
+ env->dcache_line_size = 32;
env->icache_line_size = 64;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
+/* PowerPC 601v */
+#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
+ PPC_FLOAT | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_601v (PPC_NONE)
+#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
+#define POWERPC_MSRR_601v (0x0000000000001040ULL)
+#define POWERPC_MMU_601v (POWERPC_MMU_601)
+#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
+#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
+#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
+#define check_pow_601v check_pow_none
+
+static void init_proc_601v (CPUPPCState *env)
+{
+ init_proc_601(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_601_HID15, "HID15",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* PowerPC 602 */
-#define POWERPC_INSNS_602 (POWERPC_INSNS_6xx | PPC_MFTB | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\
+#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_602_SPEC)
-#define POWERPC_MSRM_602 (0x000000000033FF73ULL)
+#define POWERPC_INSNS2_602 (PPC_NONE)
+#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
+/* XXX: 602 MMU is quite specific. Should add a special case */
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
}
/* PowerPC 603 */
-#define POWERPC_INSNS_603 (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_603 (PPC_NONE)
#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
}
/* PowerPC 603e */
-#define POWERPC_INSNS_603E (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
+#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_603E (PPC_NONE)
#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
}
/* PowerPC 604 */
-#define POWERPC_INSNS_604 (POWERPC_INSNS_WORKS | PPC_EXTERN)
+#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_604 (PPC_NONE)
#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
#define POWERPC_MMU_604 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
gen_low_BATs(env);
init_excp_604(env);
ppc6xx_irq_init(env);
}
-/* PowerPC 740/750 (aka G3) */
-#define POWERPC_INSNS_7x0 (POWERPC_INSNS_WORKS | PPC_EXTERN)
-#define POWERPC_MSRM_7x0 (0x000000000005FF77ULL)
-#define POWERPC_MMU_7x0 (POWERPC_MMU_32B)
-//#define POWERPC_EXCP_7x0 (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_7x0 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7x0 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_7x0 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+/* PowerPC 604E */
+#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_604E (PPC_NONE)
+#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
+#define POWERPC_MMU_604E (POWERPC_MMU_32B)
+#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
+#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
+#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_7x0 check_pow_hid0
+#define check_pow_604E check_pow_nocheck
-static void init_proc_7x0 (CPUPPCState *env)
+static void init_proc_604E (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_7xx(env);
+ gen_spr_604(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Time base */
gen_tbl(env);
- /* Thermal management */
- gen_spr_thrm(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
0x00000000);
/* Memory management */
gen_low_BATs(env);
- init_excp_7x0(env);
+ init_excp_604(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
-/* PowerPC 750FX/GX */
-#define POWERPC_INSNS_750fx (POWERPC_INSNS_WORKS | PPC_EXTERN)
-#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
-#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
-#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
-#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
-#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+/* PowerPC 740 */
+#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_740 (PPC_NONE)
+#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
+#define POWERPC_MMU_740 (POWERPC_MMU_32B)
+#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
+#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_750fx check_pow_hid0
+#define check_pow_740 check_pow_hid0
-static void init_proc_750fx (CPUPPCState *env)
+static void init_proc_740 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_750_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
gen_low_BATs(env);
- /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
- gen_high_BATs(env);
- init_excp_750FX(env);
+ init_excp_7x0(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
}
-/* PowerPC 745/755 */
-#define POWERPC_INSNS_7x5 (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
-#define POWERPC_MSRM_7x5 (0x000000000005FF77ULL)
-#define POWERPC_MMU_7x5 (POWERPC_MMU_SOFT_6xx)
-//#define POWERPC_EXCP_7x5 (POWERPC_EXCP_7x5)
-#define POWERPC_INPUT_7x5 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7x5 (bfd_mach_ppc_750)
-#define POWERPC_FLAG_7x5 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+/* PowerPC 750 */
+#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_750 (PPC_NONE)
+#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
+#define POWERPC_MMU_750 (POWERPC_MMU_32B)
+#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
+#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
-#define check_pow_7x5 check_pow_hid0
+#define check_pow_750 check_pow_hid0
-static void init_proc_7x5 (CPUPPCState *env)
+static void init_proc_750 (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_G2_755(env);
- /* Time base */
- gen_tbl(env);
- /* L2 cache control */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTC, "ICTC",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ gen_spr_7xx(env);
/* XXX : not implemented */
- spr_register(env, SPR_L2PMCR, "L2PMCR",
+ spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
/* Hardware implementation registers */
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
gen_low_BATs(env);
- gen_high_BATs(env);
- gen_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_7x5(env);
+ /* XXX: high BATs are also present but are known to be bugged on
+ * die version 1.x
+ */
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 750 CL */
+/* XXX: not implemented:
+ * cache lock instructions:
+ * dcbz_l
+ * floating point paired instructions
+ * psq_lux
+ * psq_lx
+ * psq_stux
+ * psq_stx
+ * ps_abs
+ * ps_add
+ * ps_cmpo0
+ * ps_cmpo1
+ * ps_cmpu0
+ * ps_cmpu1
+ * ps_div
+ * ps_madd
+ * ps_madds0
+ * ps_madds1
+ * ps_merge00
+ * ps_merge01
+ * ps_merge10
+ * ps_merge11
+ * ps_mr
+ * ps_msub
+ * ps_mul
+ * ps_muls0
+ * ps_muls1
+ * ps_nabs
+ * ps_neg
+ * ps_nmadd
+ * ps_nmsub
+ * ps_res
+ * ps_rsqrte
+ * ps_sel
+ * ps_sub
+ * ps_sum0
+ * ps_sum1
+ */
+#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_750cl (PPC_NONE)
+#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
+#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
+#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
+#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_750cl check_pow_hid0
+
+static void init_proc_750cl (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ /* Those registers are fake on 750CL */
+ spr_register(env, SPR_THRM1, "THRM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_THRM2, "THRM2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_THRM3, "THRM3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX: not implemented */
+ spr_register(env, SPR_750_TDCL, "TDCL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_TDCH, "TDCH",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* DMA */
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_WPAR, "WPAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_DMAL, "DMAL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_750_DMAU, "DMAU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750CL_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750CL_HID4, "HID4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Quantization registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR0, "GQR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR1, "GQR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR2, "GQR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR3, "GQR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR4, "GQR4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR5, "GQR5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR6, "GQR6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_GQR7, "GQR7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750cl has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_750cl(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 750CX */
+#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_750cx (PPC_NONE)
+#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
+#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
+#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
+#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_750cx check_pow_hid0
+
+static void init_proc_750cx (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* This register is not implemented but is present for compatibility */
+ spr_register(env, SPR_SDA, "SDA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750cx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_750cx(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 750FX */
+#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_750fx (PPC_NONE)
+#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
+#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
+#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
+#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_750fx check_pow_hid0
+
+static void init_proc_750fx (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_THRM4, "THRM4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750FX_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 750GX */
+#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_750gx (PPC_NONE)
+#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
+#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
+#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
+#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
+#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_750gx check_pow_hid0
+
+static void init_proc_750gx (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_750_THRM4, "THRM4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented (XXX: different from 750fx) */
+ spr_register(env, SPR_750FX_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
+ gen_high_BATs(env);
+ init_excp_7x0(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 745 */
+#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_745 (PPC_NONE)
+#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
+#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
+#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
+#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
+#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_745 check_pow_hid0
+
+static void init_proc_745 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ gen_spr_G2_755(env);
+ /* Time base */
+ gen_tbl(env);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_7x5(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 755 */
+#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN)
+#define POWERPC_INSNS2_755 (PPC_NONE)
+#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
+#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
+#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
+#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
+#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
+#define check_pow_755 check_pow_hid0
+
+static void init_proc_755 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ gen_spr_G2_755(env);
+ /* Time base */
+ gen_tbl(env);
+ /* L2 cache control */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2PMCR, "L2PMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Thermal management */
+ gen_spr_thrm(env);
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_high_BATs(env);
+ gen_6xx_7xx_soft_tlb(env, 64, 2);
+ init_excp_7x5(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
/* Allocate hardware IRQ controller */
ppc6xx_irq_init(env);
-#if !defined(CONFIG_USER_ONLY)
- /* Hardware reset vector */
- env->hreset_vector = 0xFFFFFFFCUL;
-#endif
}
/* PowerPC 7400 (aka G4) */
-#define POWERPC_INSNS_7400 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+#define POWERPC_INSNS2_7400 (PPC_NONE)
#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX: this seems not implemented on all revisions. */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSCR1, "MSSCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Thermal management */
gen_spr_thrm(env);
/* Memory management */
}
/* PowerPC 7410 (aka G4) */
-#define POWERPC_INSNS_7410 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+#define POWERPC_INSNS2_7410 (PPC_NONE)
#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
/* Thermal management */
gen_spr_thrm(env);
/* L2PMCR */
}
/* PowerPC 7440 (aka G4) */
-#define POWERPC_INSNS_7440 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+#define POWERPC_INSNS2_7440 (PPC_NONE)
#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7440 check_pow_hid0
+#define check_pow_7440 check_pow_hid0_74xx
__attribute__ (( unused ))
static void init_proc_7440 (CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
}
/* PowerPC 7450 (aka G4) */
-#define POWERPC_INSNS_7450 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+#define POWERPC_INSNS2_7450 (PPC_NONE)
#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7450 check_pow_hid0
+#define check_pow_7450 check_pow_hid0_74xx
__attribute__ (( unused ))
static void init_proc_7450 (CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
- /* Level 3 cache control */
- gen_l3_ctrl(env);
+ /* Level 3 cache control */
+ gen_l3_ctrl(env);
+ /* L3ITCR1 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR1, "L3ITCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR2 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR2, "L3ITCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR3 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR3, "L3ITCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3OHCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3OHCR, "L3OHCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UBAMR, "UBAMR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* LDSTCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_LDSTCR, "LDSTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* ICTRL */
+ /* XXX : not implemented */
+ spr_register(env, SPR_ICTRL, "ICTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* MSSSR0 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MSSSR0, "MSSSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* PMC */
+ /* XXX : not implemented */
+ spr_register(env, SPR_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* Memory management */
+ gen_low_BATs(env);
+ gen_74xx_soft_tlb(env, 128, 2);
+ init_excp_7450(env);
+ env->dcache_line_size = 32;
+ env->icache_line_size = 32;
+ /* Allocate hardware IRQ controller */
+ ppc6xx_irq_init(env);
+}
+
+/* PowerPC 7445 (aka G4) */
+#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
+ PPC_ALTIVEC)
+#define POWERPC_INSNS2_7445 (PPC_NONE)
+#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
+#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
+#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
+#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
+#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_7445 check_pow_hid0_74xx
+
+__attribute__ (( unused ))
+static void init_proc_7445 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+ /* 74xx specific SPR */
+ gen_spr_74xx(env);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
+ /* SPRGs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
/* Memory management */
gen_low_BATs(env);
+ gen_high_BATs(env);
gen_74xx_soft_tlb(env, 128, 2);
init_excp_7450(env);
env->dcache_line_size = 32;
ppc6xx_irq_init(env);
}
-/* PowerPC 7445 (aka G4) */
-#define POWERPC_INSNS_7445 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+/* PowerPC 7455 (aka G4) */
+#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
-#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
+#define POWERPC_INSNS2_7455 (PPC_NONE)
+#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
+#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
+#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
+#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
+#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7445 check_pow_hid0
+#define check_pow_7455 check_pow_hid0_74xx
__attribute__ (( unused ))
-static void init_proc_7445 (CPUPPCState *env)
+static void init_proc_7455 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ /* Level 3 cache control */
+ gen_l3_ctrl(env);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
ppc6xx_irq_init(env);
}
-/* PowerPC 7455 (aka G4) */
-#define POWERPC_INSNS_7455 (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA | \
- PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA | \
+/* PowerPC 7457 (aka G4) */
+#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | \
+ PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_MEM_TLBIA | PPC_74xx_TLB | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
-#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
-#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
-#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
+#define POWERPC_INSNS2_7457 (PPC_NONE)
+#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
+#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
+#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
+#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
+#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
+#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
POWERPC_FLAG_BUS_CLK)
-#define check_pow_7455 check_pow_hid0
+#define check_pow_7457 check_pow_hid0_74xx
__attribute__ (( unused ))
-static void init_proc_7455 (CPUPPCState *env)
+static void init_proc_7457 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
gen_spr_74xx(env);
/* Level 3 cache control */
gen_l3_ctrl(env);
+ /* L3ITCR1 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR1, "L3ITCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR2 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR2, "L3ITCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3ITCR3 */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3ITCR3, "L3ITCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* L3OHCR */
+ /* XXX : not implemented */
+ spr_register(env, SPR_L3OHCR, "L3OHCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
}
#if defined (TARGET_PPC64)
-#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \
- PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
- PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
/* PowerPC 970 */
-#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+#define POWERPC_INSNS2_970 (PPC_NONE)
#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
#define POWERPC_MMU_970 (POWERPC_MMU_64B)
//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_750_HID2, "HID2",
+ spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
POWERPC970_HID5_INIT);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
0x00000000); /* TOFIX */
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFF00000); /* XXX: This is a hack */
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970FX (aka G5) */
-#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+#define POWERPC_INSNS2_970FX (PPC_NONE)
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_750_HID2, "HID2",
+ spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
POWERPC970_HID5_INIT);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
0x00000000); /* TOFIX */
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
+ spr_register(env, SPR_CTRL, "SPR_CTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
- 0xFFF00000); /* XXX: This is a hack */
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
+ env->slb_nr = 64;
#endif
init_excp_970(env);
env->dcache_line_size = 128;
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970 GX */
-#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+#define POWERPC_INSNS2_970GX (PPC_NONE)
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_750_HID2, "HID2",
+ spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
POWERPC970_HID5_INIT);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
0x00000000); /* TOFIX */
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFF00000); /* XXX: This is a hack */
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
/* PowerPC 970 MP */
-#define POWERPC_INSNS_970MP (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+#define POWERPC_INSNS2_970MP (PPC_NONE)
#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_750_HID2, "HID2",
+ spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
POWERPC970_HID5_INIT);
+ /* XXX : not implemented */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
0x00000000); /* TOFIX */
spr_register(env, SPR_HIOR, "SPR_HIOR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFF00000); /* XXX: This is a hack */
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
+}
+
+#if defined(TARGET_PPC64)
+/* POWER7 */
+#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_64B | PPC_ALTIVEC | \
+ PPC_SEGMENT_64B | PPC_SLBI | \
+ PPC_POPCNTB | PPC_POPCNTWD)
+#define POWERPC_INSNS2_POWER7 (PPC_NONE)
+#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
+#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
+#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
+#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
+#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
+#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
+ POWERPC_FLAG_BUS_CLK)
+#define check_pow_POWER7 check_pow_nocheck
+
+static void init_proc_POWER7 (CPUPPCState *env)
+{
+ gen_spr_ne_601(env);
+ gen_spr_7xx(env);
+ /* Time base */
+ gen_tbl(env);
+#if !defined(CONFIG_USER_ONLY)
+ /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
+ spr_register(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ 0x00000000);
+#endif /* !CONFIG_USER_ONLY */
+ /* Memory management */
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMUCFG, "MMUCFG",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000); /* TOFIX */
+ /* XXX : not implemented */
+ spr_register(env, SPR_CTRL, "SPR_CTRLT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x80800000);
+ spr_register(env, SPR_UCTRL, "SPR_CTRLF",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x80800000);
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#if !defined(CONFIG_USER_ONLY)
+ env->slb_nr = 32;
+#endif
+ init_excp_POWER7(env);
+ env->dcache_line_size = 128;
+ env->icache_line_size = 128;
+ /* Allocate hardware IRQ controller */
+ ppcPOWER7_irq_init(env);
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
}
+#endif /* TARGET_PPC64 */
/* PowerPC 620 */
-#define POWERPC_INSNS_620 (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT | \
+#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
+ PPC_FLOAT_STFIWX | \
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
+ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
+ PPC_SEGMENT | PPC_EXTERN | \
PPC_64B | PPC_SLBI)
-#define POWERPC_MSRM_620 (0x800000000005FF73ULL)
-#define POWERPC_MMU_620 (POWERPC_MMU_64B)
+#define POWERPC_INSNS2_620 (PPC_NONE)
+#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
+//#define POWERPC_MMU_620 (POWERPC_MMU_620)
#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
#define POWERPC_BFDM_620 (bfd_mach_ppc64)
#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
- POWERPC_FLAG_BUS_CLK)
+ POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
#define check_pow_620 check_pow_nocheck /* Check this */
__attribute__ (( unused ))
0x00000000);
/* Memory management */
gen_low_BATs(env);
- gen_high_BATs(env);
init_excp_620(env);
env->dcache_line_size = 64;
env->icache_line_size = 64;
/* Default 32 bits PowerPC target will be 604 */
#define CPU_POWERPC_PPC32 CPU_POWERPC_604
#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
+#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
#define POWERPC_MMU_PPC32 POWERPC_MMU_604
#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
/* Default 64 bits PowerPC target will be 970 FX */
#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
+#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
/* Default PowerPC target will be PowerPC 32 */
#if defined (TARGET_PPC64) && 0 // XXX: TODO
-#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
-#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
-#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
-#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
-#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
-#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
-#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
-#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
-#define check_pow_DEFAULT check_pow_PPC64
-#define init_proc_DEFAULT init_proc_PPC64
+#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
+#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
+#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
+#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
+#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
+#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
+#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
+#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
+#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
+#define check_pow_DEFAULT check_pow_PPC64
+#define init_proc_DEFAULT init_proc_PPC64
#else
-#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
-#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
-#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
-#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
-#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
-#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
-#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
-#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
-#define check_pow_DEFAULT check_pow_PPC32
-#define init_proc_DEFAULT init_proc_PPC32
+#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
+#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
+#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
+#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
+#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
+#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
+#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
+#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
+#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
+#define check_pow_DEFAULT check_pow_PPC32
+#define init_proc_DEFAULT init_proc_PPC32
#endif
/*****************************************************************************/
#if 0
CPU_POWERPC_440A4 = xxx,
#endif
+ CPU_POWERPC_440_XILINX = 0x7ff21910,
#if 0
CPU_POWERPC_440A5 = xxx,
#endif
CPU_POWERPC_e300c3 = 0x00850010,
CPU_POWERPC_e300c4 = 0x00860010,
/* MPC83xx microcontrollers */
-#define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
-#define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
-#define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
-#define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
-#define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
+#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
+#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
+#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
+#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
/* e500 family */
/* e500 cores */
#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
+#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
- CPU_POWERPC_e500_v10 = 0x80200010,
- CPU_POWERPC_e500_v20 = 0x80200020,
+ CPU_POWERPC_e500v1_v10 = 0x80200010,
+ CPU_POWERPC_e500v1_v20 = 0x80200020,
CPU_POWERPC_e500v2_v10 = 0x80210010,
CPU_POWERPC_e500v2_v11 = 0x80210011,
CPU_POWERPC_e500v2_v20 = 0x80210020,
#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
-#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
-#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
+#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
-#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
-#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
-#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
+#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
+#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
#define CPU_POWERPC_601 CPU_POWERPC_601_v2
CPU_POWERPC_601_v0 = 0x00010001,
CPU_POWERPC_601_v1 = 0x00010001,
+#define CPU_POWERPC_601v CPU_POWERPC_601_v2
CPU_POWERPC_601_v2 = 0x00010002,
CPU_POWERPC_602 = 0x00050100,
CPU_POWERPC_603 = 0x00030100,
/* PowerPC 740/750 cores (aka G3) */
/* XXX: missing 0x00084202 */
#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
+ CPU_POWERPC_7x0_v10 = 0x00080100,
CPU_POWERPC_7x0_v20 = 0x00080200,
CPU_POWERPC_7x0_v21 = 0x00080201,
CPU_POWERPC_7x0_v22 = 0x00080202,
CPU_POWERPC_7x0_v30 = 0x00080300,
CPU_POWERPC_7x0_v31 = 0x00080301,
CPU_POWERPC_740E = 0x00080100,
+ CPU_POWERPC_750E = 0x00080200,
CPU_POWERPC_7x0P = 0x10080000,
/* XXX: missing 0x00087010 (CL ?) */
- CPU_POWERPC_750CL = 0x00087200,
+#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
+ CPU_POWERPC_750CL_v10 = 0x00087200,
+ CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
+ CPU_POWERPC_750CX_v10 = 0x00082100,
+ CPU_POWERPC_750CX_v20 = 0x00082200,
CPU_POWERPC_750CX_v21 = 0x00082201,
CPU_POWERPC_750CX_v22 = 0x00082202,
#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
CPU_POWERPC_750CXE_v23 = 0x00082213,
CPU_POWERPC_750CXE_v24 = 0x00082214,
CPU_POWERPC_750CXE_v24b = 0x00083214,
- CPU_POWERPC_750CXE_v31 = 0x00083211,
+ CPU_POWERPC_750CXE_v30 = 0x00082310,
+ CPU_POWERPC_750CXE_v31 = 0x00082311,
CPU_POWERPC_750CXE_v31b = 0x00083311,
CPU_POWERPC_750CXR = 0x00083410,
- CPU_POWERPC_750E = 0x00080200,
- CPU_POWERPC_750FL = 0x700A0203,
+ CPU_POWERPC_750FL = 0x70000203,
#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
CPU_POWERPC_750FX_v10 = 0x70000100,
CPU_POWERPC_750FX_v20 = 0x70000200,
CPU_POWERPC_750GX_v11 = 0x70020101,
CPU_POWERPC_750GX_v12 = 0x70020102,
#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
+ CPU_POWERPC_750L_v20 = 0x00088200,
+ CPU_POWERPC_750L_v21 = 0x00088201,
CPU_POWERPC_750L_v22 = 0x00088202,
CPU_POWERPC_750L_v30 = 0x00088300,
CPU_POWERPC_750L_v32 = 0x00088302,
CPU_POWERPC_7400_v10 = 0x000C0100,
CPU_POWERPC_7400_v11 = 0x000C0101,
CPU_POWERPC_7400_v20 = 0x000C0200,
+ CPU_POWERPC_7400_v21 = 0x000C0201,
CPU_POWERPC_7400_v22 = 0x000C0202,
CPU_POWERPC_7400_v26 = 0x000C0206,
CPU_POWERPC_7400_v27 = 0x000C0207,
CPU_POWERPC_7450_v10 = 0x80000100,
CPU_POWERPC_7450_v11 = 0x80000101,
CPU_POWERPC_7450_v12 = 0x80000102,
- CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
+ CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
- CPU_POWERPC_74x1 = 0x80000203,
- CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
+#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
+ CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
+ /* XXX: this entry might be a bug in some documentation */
+ CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
CPU_POWERPC_74x5_v10 = 0x80010100,
/* XXX: missing 0x80010200 */
CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
- /* XXX: is 0x8002xxxx 7447 and 0x8003xxxx 7457 ? */
- /* XXX: missing 0x80030102 */
- /* XXX: missing 0x80020101 */
CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
- CPU_POWERPC_74x7_v11 = 0x80030101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
+#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
+ CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
+ CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
+ CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
/* 64 bits PowerPC */
#if defined(TARGET_PPC64)
CPU_POWERPC_620 = 0x00140000,
CPU_POWERPC_POWER6 = 0x003E0000,
CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
CPU_POWERPC_POWER6A = 0x0F000002,
+#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
+ CPU_POWERPC_POWER7_v20 = 0x003F0200,
CPU_POWERPC_970 = 0x00390202,
#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
CPU_POWERPC_970FX_v10 = 0x00391100,
#if 0
POWERPC_SVR_8323E = xxx,
#endif
+ POWERPC_SVR_8343 = 0x80570010,
POWERPC_SVR_8343A = 0x80570030,
+ POWERPC_SVR_8343E = 0x80560010,
POWERPC_SVR_8343EA = 0x80560030,
+#define POWERPC_SVR_8347 POWERPC_SVR_8347T
+ POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
+ POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
+#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
+ POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
+ POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
/* PowerPC CPU definitions */
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
{ \
- .name = _name, \
- .pvr = _pvr, \
- .svr = _svr, \
- .insns_flags = glue(POWERPC_INSNS_,_type), \
- .msr_mask = glue(POWERPC_MSRM_,_type), \
- .mmu_model = glue(POWERPC_MMU_,_type), \
- .excp_model = glue(POWERPC_EXCP_,_type), \
- .bus_model = glue(POWERPC_INPUT_,_type), \
- .bfd_mach = glue(POWERPC_BFDM_,_type), \
- .flags = glue(POWERPC_FLAG_,_type), \
- .init_proc = &glue(init_proc_,_type), \
- .check_pow = &glue(check_pow_,_type), \
+ .name = _name, \
+ .pvr = _pvr, \
+ .svr = _svr, \
+ .insns_flags = glue(POWERPC_INSNS_,_type), \
+ .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
+ .msr_mask = glue(POWERPC_MSRM_,_type), \
+ .mmu_model = glue(POWERPC_MMU_,_type), \
+ .excp_model = glue(POWERPC_EXCP_,_type), \
+ .bus_model = glue(POWERPC_INPUT_,_type), \
+ .bfd_mach = glue(POWERPC_BFDM_,_type), \
+ .flags = glue(POWERPC_FLAG_,_type), \
+ .init_proc = &glue(init_proc_,_type), \
+ .check_pow = &glue(check_pow_,_type), \
}
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
/* PowerPC 440 A4 */
POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
#endif
+ /* PowerPC 440 Xilinx 5 */
+ POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
#if defined (TODO)
/* PowerPC 440 A5 */
POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
/* MPC8240 */
POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
/* PowerPC G2 microcontrollers */
-#if 0
+#if defined(TODO)
/* MPC5121 */
POWERPC_DEF_SVR("MPC5121",
CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
#if defined (TODO)
/* MPC8313 */
POWERPC_DEF_SVR("MPC8313",
- CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
#endif
#if defined (TODO)
/* MPC8313E */
POWERPC_DEF_SVR("MPC8313E",
- CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
#endif
#if defined (TODO)
/* MPC8314 */
POWERPC_DEF_SVR("MPC8314",
- CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
#endif
#if defined (TODO)
/* MPC8314E */
POWERPC_DEF_SVR("MPC8314E",
- CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
#endif
#if defined (TODO)
/* MPC8315 */
POWERPC_DEF_SVR("MPC8315",
- CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
#endif
#if defined (TODO)
/* MPC8315E */
POWERPC_DEF_SVR("MPC8315E",
- CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
+ CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
#endif
#if defined (TODO)
/* MPC8321 */
POWERPC_DEF_SVR("MPC8321",
- CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
#endif
#if defined (TODO)
/* MPC8321E */
POWERPC_DEF_SVR("MPC8321E",
- CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
#endif
#if defined (TODO)
/* MPC8323 */
POWERPC_DEF_SVR("MPC8323",
- CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
#endif
#if defined (TODO)
/* MPC8323E */
POWERPC_DEF_SVR("MPC8323E",
- CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
+ CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
#endif
+ /* MPC8343 */
+ POWERPC_DEF_SVR("MPC8343",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
/* MPC8343A */
POWERPC_DEF_SVR("MPC8343A",
- CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
+ /* MPC8343E */
+ POWERPC_DEF_SVR("MPC8343E",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
/* MPC8343EA */
POWERPC_DEF_SVR("MPC8343EA",
- CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
+ /* MPC8347 */
+ POWERPC_DEF_SVR("MPC8347",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
+ /* MPC8347T */
+ POWERPC_DEF_SVR("MPC8347T",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
+ /* MPC8347P */
+ POWERPC_DEF_SVR("MPC8347P",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
/* MPC8347A */
POWERPC_DEF_SVR("MPC8347A",
- CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
/* MPC8347AT */
POWERPC_DEF_SVR("MPC8347AT",
- CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
/* MPC8347AP */
POWERPC_DEF_SVR("MPC8347AP",
- CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
+ /* MPC8347E */
+ POWERPC_DEF_SVR("MPC8347E",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
+ /* MPC8347ET */
+ POWERPC_DEF_SVR("MPC8347ET",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
+ /* MPC8343EP */
+ POWERPC_DEF_SVR("MPC8347EP",
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
/* MPC8347EA */
POWERPC_DEF_SVR("MPC8347EA",
- CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
/* MPC8347EAT */
POWERPC_DEF_SVR("MPC8347EAT",
- CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
/* MPC8343EAP */
POWERPC_DEF_SVR("MPC8347EAP",
- CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
/* MPC8349 */
POWERPC_DEF_SVR("MPC8349",
- CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
/* MPC8349A */
POWERPC_DEF_SVR("MPC8349A",
- CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
/* MPC8349E */
POWERPC_DEF_SVR("MPC8349E",
- CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
/* MPC8349EA */
POWERPC_DEF_SVR("MPC8349EA",
- CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
+ CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
#if defined (TODO)
/* MPC8358E */
POWERPC_DEF_SVR("MPC8358E",
- CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
+ CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
#endif
#if defined (TODO)
/* MPC8360E */
POWERPC_DEF_SVR("MPC8360E",
- CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
+ CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
#endif
/* MPC8377 */
POWERPC_DEF_SVR("MPC8377",
- CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
/* MPC8377E */
POWERPC_DEF_SVR("MPC8377E",
- CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
/* MPC8378 */
POWERPC_DEF_SVR("MPC8378",
- CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
/* MPC8378E */
POWERPC_DEF_SVR("MPC8378E",
- CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
/* MPC8379 */
POWERPC_DEF_SVR("MPC8379",
- CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
/* MPC8379E */
POWERPC_DEF_SVR("MPC8379E",
- CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
+ CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
/* e500 family */
/* PowerPC e500 core */
- POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
+ POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
+ /* PowerPC e500v1 core */
+ POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
/* PowerPC e500 v1.0 core */
- POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
+ POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
/* PowerPC e500 v2.0 core */
- POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
+ POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
/* PowerPC e500v2 core */
- POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
+ POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
/* PowerPC e500v2 v1.0 core */
- POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
+ POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
/* PowerPC e500v2 v2.0 core */
- POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
+ POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
/* PowerPC e500v2 v2.1 core */
- POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
+ POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
/* PowerPC e500v2 v2.2 core */
- POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
+ POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
/* PowerPC e500v2 v3.0 core */
- POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
+ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
/* PowerPC e500 microcontrollers */
/* MPC8533 */
POWERPC_DEF_SVR("MPC8533",
- CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
+ CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
/* MPC8533 v1.0 */
POWERPC_DEF_SVR("MPC8533_v10",
- CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
+ CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
/* MPC8533 v1.1 */
POWERPC_DEF_SVR("MPC8533_v11",
- CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
+ CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
/* MPC8533E */
POWERPC_DEF_SVR("MPC8533E",
- CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
+ CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
/* MPC8533E v1.0 */
POWERPC_DEF_SVR("MPC8533E_v10",
- CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
+ CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
POWERPC_DEF_SVR("MPC8533E_v11",
- CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
+ CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
/* MPC8540 */
POWERPC_DEF_SVR("MPC8540",
- CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
+ CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
/* MPC8540 v1.0 */
POWERPC_DEF_SVR("MPC8540_v10",
- CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
+ CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
/* MPC8540 v2.0 */
POWERPC_DEF_SVR("MPC8540_v20",
- CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
+ CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
/* MPC8540 v2.1 */
POWERPC_DEF_SVR("MPC8540_v21",
- CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
+ CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
/* MPC8541 */
POWERPC_DEF_SVR("MPC8541",
- CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
+ CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
/* MPC8541 v1.0 */
POWERPC_DEF_SVR("MPC8541_v10",
- CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
+ CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
/* MPC8541 v1.1 */
POWERPC_DEF_SVR("MPC8541_v11",
- CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
+ CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
/* MPC8541E */
POWERPC_DEF_SVR("MPC8541E",
- CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
+ CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
/* MPC8541E v1.0 */
POWERPC_DEF_SVR("MPC8541E_v10",
- CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
+ CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
/* MPC8541E v1.1 */
POWERPC_DEF_SVR("MPC8541E_v11",
- CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
+ CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
/* MPC8543 */
POWERPC_DEF_SVR("MPC8543",
- CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
+ CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
/* MPC8543 v1.0 */
POWERPC_DEF_SVR("MPC8543_v10",
- CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
+ CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
/* MPC8543 v1.1 */
POWERPC_DEF_SVR("MPC8543_v11",
- CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
+ CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
/* MPC8543 v2.0 */
POWERPC_DEF_SVR("MPC8543_v20",
- CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
+ CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
/* MPC8543 v2.1 */
POWERPC_DEF_SVR("MPC8543_v21",
- CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
+ CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
/* MPC8543E */
POWERPC_DEF_SVR("MPC8543E",
- CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
+ CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
/* MPC8543E v1.0 */
POWERPC_DEF_SVR("MPC8543E_v10",
- CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
+ CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
/* MPC8543E v1.1 */
POWERPC_DEF_SVR("MPC8543E_v11",
- CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
+ CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
/* MPC8543E v2.0 */
POWERPC_DEF_SVR("MPC8543E_v20",
- CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
+ CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
/* MPC8543E v2.1 */
POWERPC_DEF_SVR("MPC8543E_v21",
- CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
+ CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
/* MPC8544 */
POWERPC_DEF_SVR("MPC8544",
- CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
+ CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
/* MPC8544 v1.0 */
POWERPC_DEF_SVR("MPC8544_v10",
- CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
+ CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
/* MPC8544 v1.1 */
POWERPC_DEF_SVR("MPC8544_v11",
- CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
+ CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
/* MPC8544E */
POWERPC_DEF_SVR("MPC8544E",
- CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
+ CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
/* MPC8544E v1.0 */
POWERPC_DEF_SVR("MPC8544E_v10",
- CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
+ CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
/* MPC8544E v1.1 */
POWERPC_DEF_SVR("MPC8544E_v11",
- CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
+ CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
/* MPC8545 */
POWERPC_DEF_SVR("MPC8545",
- CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
+ CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
/* MPC8545 v2.0 */
POWERPC_DEF_SVR("MPC8545_v20",
- CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
+ CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
/* MPC8545 v2.1 */
POWERPC_DEF_SVR("MPC8545_v21",
- CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
+ CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
/* MPC8545E */
POWERPC_DEF_SVR("MPC8545E",
- CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
+ CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
/* MPC8545E v2.0 */
POWERPC_DEF_SVR("MPC8545E_v20",
- CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
+ CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
/* MPC8545E v2.1 */
POWERPC_DEF_SVR("MPC8545E_v21",
- CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
+ CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
/* MPC8547E */
POWERPC_DEF_SVR("MPC8547E",
- CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
+ CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
/* MPC8547E v2.0 */
POWERPC_DEF_SVR("MPC8547E_v20",
- CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
+ CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
/* MPC8547E v2.1 */
POWERPC_DEF_SVR("MPC8547E_v21",
- CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
+ CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
/* MPC8548 */
POWERPC_DEF_SVR("MPC8548",
- CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
+ CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
/* MPC8548 v1.0 */
POWERPC_DEF_SVR("MPC8548_v10",
- CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
+ CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
/* MPC8548 v1.1 */
POWERPC_DEF_SVR("MPC8548_v11",
- CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
+ CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
/* MPC8548 v2.0 */
POWERPC_DEF_SVR("MPC8548_v20",
- CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
+ CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
/* MPC8548 v2.1 */
POWERPC_DEF_SVR("MPC8548_v21",
- CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
+ CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
/* MPC8548E */
POWERPC_DEF_SVR("MPC8548E",
- CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
+ CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
/* MPC8548E v1.0 */
POWERPC_DEF_SVR("MPC8548E_v10",
- CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
+ CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
/* MPC8548E v1.1 */
POWERPC_DEF_SVR("MPC8548E_v11",
- CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
+ CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
/* MPC8548E v2.0 */
POWERPC_DEF_SVR("MPC8548E_v20",
- CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
+ CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
/* MPC8548E v2.1 */
POWERPC_DEF_SVR("MPC8548E_v21",
- CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
+ CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
/* MPC8555 */
POWERPC_DEF_SVR("MPC8555",
- CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
+ CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
/* MPC8555 v1.0 */
POWERPC_DEF_SVR("MPC8555_v10",
- CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
+ CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
/* MPC8555 v1.1 */
POWERPC_DEF_SVR("MPC8555_v11",
- CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
+ CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
/* MPC8555E */
POWERPC_DEF_SVR("MPC8555E",
- CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
+ CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
/* MPC8555E v1.0 */
POWERPC_DEF_SVR("MPC8555E_v10",
- CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
+ CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
/* MPC8555E v1.1 */
POWERPC_DEF_SVR("MPC8555E_v11",
- CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
+ CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
/* MPC8560 */
POWERPC_DEF_SVR("MPC8560",
- CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
+ CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
/* MPC8560 v1.0 */
POWERPC_DEF_SVR("MPC8560_v10",
- CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
+ CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
/* MPC8560 v2.0 */
POWERPC_DEF_SVR("MPC8560_v20",
- CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
+ CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
/* MPC8560 v2.1 */
POWERPC_DEF_SVR("MPC8560_v21",
- CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
+ CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
/* MPC8567 */
POWERPC_DEF_SVR("MPC8567",
- CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
+ CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
/* MPC8567E */
POWERPC_DEF_SVR("MPC8567E",
- CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
+ CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
/* MPC8568 */
POWERPC_DEF_SVR("MPC8568",
- CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
+ CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
/* MPC8568E */
POWERPC_DEF_SVR("MPC8568E",
- CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
+ CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
/* MPC8572 */
POWERPC_DEF_SVR("MPC8572",
- CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
+ CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
/* MPC8572E */
POWERPC_DEF_SVR("MPC8572E",
- CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
+ CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
/* e600 family */
/* PowerPC e600 core */
POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
/* PowerPC 601 */
- POWERPC_DEF("601", CPU_POWERPC_601, 601),
+ POWERPC_DEF("601", CPU_POWERPC_601, 601v),
/* PowerPC 601v0 */
- POWERPC_DEF("601v0", CPU_POWERPC_601_v0, 601),
+ POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
/* PowerPC 601v1 */
- POWERPC_DEF("601v1", CPU_POWERPC_601_v1, 601),
+ POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
+ /* PowerPC 601v */
+ POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
/* PowerPC 601v2 */
- POWERPC_DEF("601v2", CPU_POWERPC_601_v2, 601),
+ POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
/* PowerPC 602 */
POWERPC_DEF("602", CPU_POWERPC_602, 602),
/* PowerPC 603 */
POWERPC_DEF("603", CPU_POWERPC_603, 603),
/* Code name for PowerPC 603 */
POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
- /* PowerPC 603e */
+ /* PowerPC 603e (aka PID6) */
POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
/* Code name for PowerPC 603e */
POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
/* PowerPC 603e v4.1 */
POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
- /* PowerPC 603e */
+ /* PowerPC 603e (aka PID7) */
POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
/* PowerPC 603e7t */
POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
/* PowerPC 603e7v2 */
POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
- /* PowerPC 603p */
- /* to be checked */
- POWERPC_DEF("603p", CPU_POWERPC_603P, 603),
- /* PowerPC 603r */
+ /* PowerPC 603p (aka PID7v) */
+ POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
+ /* PowerPC 603r (aka PID7t) */
POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
/* Code name for PowerPC 603r */
POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
/* PowerPC 604 */
POWERPC_DEF("604", CPU_POWERPC_604, 604),
- /* PowerPC 604e */
- /* XXX: code names "Sirocco" "Mach 5" */
- POWERPC_DEF("604e", CPU_POWERPC_604E, 604),
+ /* PowerPC 604e (aka PID9) */
+ POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
+ /* Code name for PowerPC 604e */
+ POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
/* PowerPC 604e v1.0 */
- POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604),
+ POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
/* PowerPC 604e v2.2 */
- POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604),
+ POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
/* PowerPC 604e v2.4 */
- POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604),
- /* PowerPC 604r */
- POWERPC_DEF("604r", CPU_POWERPC_604R, 604),
+ POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
+ /* PowerPC 604r (aka PIDA) */
+ POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
+ /* Code name for PowerPC 604r */
+ POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
#if defined(TODO)
/* PowerPC 604ev */
- POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604),
+ POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
#endif
/* PowerPC 7xx family */
/* Generic PowerPC 740 (G3) */
- POWERPC_DEF("740", CPU_POWERPC_7x0, 7x0),
+ POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
+ /* Code name for PowerPC 740 */
+ POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
/* Generic PowerPC 750 (G3) */
- POWERPC_DEF("750", CPU_POWERPC_7x0, 7x0),
- /* Code name for generic PowerPC 740/750 (G3) */
- POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 7x0),
- /* XXX: 750 codename "Typhoon" */
+ POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
+ /* Code name for PowerPC 750 */
+ POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
/* PowerPC 740/750 is also known as G3 */
- POWERPC_DEF("G3", CPU_POWERPC_7x0, 7x0),
+ POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
+ /* PowerPC 740 v1.0 (G3) */
+ POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
+ /* PowerPC 750 v1.0 (G3) */
+ POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
/* PowerPC 740 v2.0 (G3) */
- POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 7x0),
+ POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
/* PowerPC 750 v2.0 (G3) */
- POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 7x0),
+ POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
/* PowerPC 740 v2.1 (G3) */
- POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 7x0),
+ POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
/* PowerPC 750 v2.1 (G3) */
- POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 7x0),
+ POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
/* PowerPC 740 v2.2 (G3) */
- POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 7x0),
+ POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
/* PowerPC 750 v2.2 (G3) */
- POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 7x0),
+ POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
/* PowerPC 740 v3.0 (G3) */
- POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 7x0),
+ POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
/* PowerPC 750 v3.0 (G3) */
- POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 7x0),
+ POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
/* PowerPC 740 v3.1 (G3) */
- POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 7x0),
+ POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
/* PowerPC 750 v3.1 (G3) */
- POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 7x0),
+ POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
/* PowerPC 740E (G3) */
- POWERPC_DEF("740e", CPU_POWERPC_740E, 7x0),
+ POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
+ /* PowerPC 750E (G3) */
+ POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
/* PowerPC 740P (G3) */
- POWERPC_DEF("740p", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
/* PowerPC 750P (G3) */
- POWERPC_DEF("750p", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
/* Code name for PowerPC 740P/750P (G3) */
- POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 7x0),
+ POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
/* PowerPC 750CL (G3 embedded) */
- POWERPC_DEF("750cl", CPU_POWERPC_750CL, 7x0),
+ POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
+ /* PowerPC 750CL v1.0 */
+ POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
+ /* PowerPC 750CL v2.0 */
+ POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
/* PowerPC 750CX (G3 embedded) */
- POWERPC_DEF("750cx", CPU_POWERPC_750CX, 7x0),
+ POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
+ /* PowerPC 750CX v1.0 (G3 embedded) */
+ POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
+ /* PowerPC 750CX v2.1 (G3 embedded) */
+ POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
/* PowerPC 750CX v2.1 (G3 embedded) */
- POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 7x0),
+ POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
/* PowerPC 750CX v2.2 (G3 embedded) */
- POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 7x0),
+ POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
/* PowerPC 750CXe (G3 embedded) */
- POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 7x0),
+ POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
/* PowerPC 750CXe v2.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v21", CPU_POWERPC_750CXE_v21, 7x0),
+ POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
/* PowerPC 750CXe v2.2 (G3 embedded) */
- POWERPC_DEF("750cxe_v22", CPU_POWERPC_750CXE_v22, 7x0),
+ POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
/* PowerPC 750CXe v2.3 (G3 embedded) */
- POWERPC_DEF("750cxe_v23", CPU_POWERPC_750CXE_v23, 7x0),
+ POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
/* PowerPC 750CXe v2.4 (G3 embedded) */
- POWERPC_DEF("750cxe_v24", CPU_POWERPC_750CXE_v24, 7x0),
+ POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
/* PowerPC 750CXe v2.4b (G3 embedded) */
- POWERPC_DEF("750cxe_v24b", CPU_POWERPC_750CXE_v24b, 7x0),
+ POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
+ /* PowerPC 750CXe v3.0 (G3 embedded) */
+ POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
/* PowerPC 750CXe v3.1 (G3 embedded) */
- POWERPC_DEF("750cxe_v31", CPU_POWERPC_750CXE_v31, 7x0),
+ POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
/* PowerPC 750CXe v3.1b (G3 embedded) */
- POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 7x0),
+ POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
/* PowerPC 750CXr (G3 embedded) */
- POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 7x0),
- /* PowerPC 750E (G3) */
- POWERPC_DEF("750e", CPU_POWERPC_750E, 7x0),
+ POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
/* PowerPC 750FL (G3 embedded) */
POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
/* PowerPC 750FX (G3 embedded) */
/* PowerPC 750FX v2.3 (G3 embedded) */
POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
/* PowerPC 750GL (G3 embedded) */
- POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750fx),
+ POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
/* PowerPC 750GX (G3 embedded) */
- POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750fx),
+ POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
/* PowerPC 750GX v1.0 (G3 embedded) */
- POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750fx),
+ POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
/* PowerPC 750GX v1.1 (G3 embedded) */
- POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750fx),
+ POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
/* PowerPC 750GX v1.2 (G3 embedded) */
- POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750fx),
+ POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
/* PowerPC 750L (G3 embedded) */
- POWERPC_DEF("750l", CPU_POWERPC_750L, 7x0),
+ POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
/* Code name for PowerPC 750L (G3 embedded) */
- POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 7x0),
+ POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
+ /* PowerPC 750L v2.0 (G3 embedded) */
+ POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
+ /* PowerPC 750L v2.1 (G3 embedded) */
+ POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
/* PowerPC 750L v2.2 (G3 embedded) */
- POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 7x0),
+ POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
/* PowerPC 750L v3.0 (G3 embedded) */
- POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 7x0),
+ POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
/* PowerPC 750L v3.2 (G3 embedded) */
- POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 7x0),
+ POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
/* Generic PowerPC 745 */
- POWERPC_DEF("745", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
/* Generic PowerPC 755 */
- POWERPC_DEF("755", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
/* Code name for PowerPC 745/755 */
- POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 7x5),
+ POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
/* PowerPC 745 v1.0 */
- POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 7x5),
+ POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
/* PowerPC 755 v1.0 */
- POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 7x5),
+ POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
/* PowerPC 745 v1.1 */
- POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 7x5),
+ POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
/* PowerPC 755 v1.1 */
- POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 7x5),
+ POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
/* PowerPC 745 v2.0 */
- POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 7x5),
+ POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
/* PowerPC 755 v2.0 */
- POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 7x5),
+ POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
/* PowerPC 745 v2.1 */
- POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 7x5),
+ POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
/* PowerPC 755 v2.1 */
- POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 7x5),
+ POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
/* PowerPC 745 v2.2 */
- POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 7x5),
+ POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
/* PowerPC 755 v2.2 */
- POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 7x5),
+ POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
/* PowerPC 745 v2.3 */
- POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 7x5),
+ POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
/* PowerPC 755 v2.3 */
- POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 7x5),
+ POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
/* PowerPC 745 v2.4 */
- POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 7x5),
+ POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
/* PowerPC 755 v2.4 */
- POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 7x5),
+ POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
/* PowerPC 745 v2.5 */
- POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 7x5),
+ POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
/* PowerPC 755 v2.5 */
- POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 7x5),
+ POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
/* PowerPC 745 v2.6 */
- POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 7x5),
+ POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
/* PowerPC 755 v2.6 */
- POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 7x5),
+ POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
/* PowerPC 745 v2.7 */
- POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 7x5),
+ POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
/* PowerPC 755 v2.7 */
- POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 7x5),
+ POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
/* PowerPC 745 v2.8 */
- POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 7x5),
+ POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
/* PowerPC 755 v2.8 */
- POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 7x5),
+ POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
#if defined (TODO)
/* PowerPC 745P (G3) */
- POWERPC_DEF("745p", CPU_POWERPC_7x5P, 7x5),
+ POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
/* PowerPC 755P (G3) */
- POWERPC_DEF("755p", CPU_POWERPC_7x5P, 7x5),
+ POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
#endif
/* PowerPC 74xx family */
/* PowerPC 7400 (G4) */
POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
/* PowerPC 7400 v2.0 (G4) */
POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
+ /* PowerPC 7400 v2.1 (G4) */
+ POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
/* PowerPC 7400 v2.2 (G4) */
POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
/* PowerPC 7400 v2.6 (G4) */
POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
/* PowerPC 7451 (G4) */
POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
- /* PowerPC 7441g (G4) */
- POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
- /* PowerPC 7451g (G4) */
- POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
+ /* PowerPC 7441 v2.1 (G4) */
+ POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
+ /* PowerPC 7441 v2.3 (G4) */
+ POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
+ /* PowerPC 7451 v2.3 (G4) */
+ POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
+ /* PowerPC 7441 v2.10 (G4) */
+ POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
+ /* PowerPC 7451 v2.10 (G4) */
+ POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
/* PowerPC 7445 (G4) */
POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
/* PowerPC 7455 (G4) */
POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
/* PowerPC 7457 v1.0 (G4) */
POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
- /* Code name for PowerPC 7447A/7457A */
- POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7_v10, 7455),
/* PowerPC 7447 v1.1 (G4) */
POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
/* PowerPC 7457 v1.1 (G4) */
POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
- /* PowerPC 7447 v1.2 (G4) */
- POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
/* PowerPC 7457 v1.2 (G4) */
POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
+ /* PowerPC 7447A (G4) */
+ POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
+ /* PowerPC 7457A (G4) */
+ POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
+ /* PowerPC 7447A v1.0 (G4) */
+ POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
+ /* PowerPC 7457A v1.0 (G4) */
+ POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
+ /* Code name for PowerPC 7447A/7457A */
+ POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
+ /* PowerPC 7447A v1.1 (G4) */
+ POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
+ /* PowerPC 7457A v1.1 (G4) */
+ POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
+ /* PowerPC 7447A v1.2 (G4) */
+ POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
+ /* PowerPC 7457A v1.2 (G4) */
+ POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
/* 64 bits PowerPC */
#if defined (TARGET_PPC64)
/* PowerPC 620 */
- /* XXX: code name "Trident" */
POWERPC_DEF("620", CPU_POWERPC_620, 620),
+ /* Code name for PowerPC 620 */
+ POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
#if defined (TODO)
/* PowerPC 630 (POWER3) */
- /* XXX: code names: "Boxer" "Dino" */
POWERPC_DEF("630", CPU_POWERPC_630, 630),
POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
+ /* Code names for POWER3 */
+ POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
+ POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
#endif
#if defined (TODO)
/* PowerPC 631 (Power 3+) */
/* POWER6A */
POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
#endif
+ /* POWER7 */
+ POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
+ POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
/* PowerPC 970 */
POWERPC_DEF("970", CPU_POWERPC_970, 970),
/* PowerPC 970FX (G5) */
};
/*****************************************************************************/
-/* Generic CPU instanciation routine */
+/* Generic CPU instantiation routine */
static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
{
#if !defined(CONFIG_USER_ONLY)
/* Set all exception vectors to an invalid address */
for (i = 0; i < POWERPC_EXCP_NB; i++)
env->excp_vectors[i] = (target_ulong)(-1ULL);
- env->excp_prefix = 0x00000000;
+ env->hreset_excp_prefix = 0x00000000;
env->ivor_mask = 0x00000000;
env->ivpr_mask = 0x00000000;
/* Default MMU definitions */
env->nb_BATs = 0;
env->nb_tlb = 0;
env->nb_ways = 0;
+ env->tlb_type = TLB_NONE;
#endif
/* Register SPR common to all PowerPC implementations */
gen_spr_generic(env);
spr_register(env, SPR_PVR, "PVR",
- SPR_NOACCESS, SPR_NOACCESS,
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
def->pvr);
/* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
}
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*def->init_proc)(env);
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_prefix = env->hreset_excp_prefix;
+#endif
/* MSR bits & flags consistency checks */
if (env->msr_mask & (1 << 25)) {
switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
int nb_tlb = env->nb_tlb;
if (env->id_tlbs != 0)
nb_tlb *= 2;
- env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
+ switch (env->tlb_type) {
+ case TLB_6XX:
+ env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
+ break;
+ case TLB_EMB:
+ env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
+ break;
+ case TLB_MAS:
+ env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
+ break;
+ }
/* Pre-compute some useful values */
env->tlb_per_way = env->nb_tlb / env->nb_ways;
}
#include <stdlib.h>
#include <string.h>
-int fflush (FILE *stream);
-
/* Opcode types */
enum {
PPC_DIRECT = 0, /* Opcode routine */
opc_handler_t **tmp;
tmp = malloc(0x20 * sizeof(opc_handler_t));
- if (tmp == NULL)
- return -1;
fill_new_table(tmp, 0x20);
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
/*****************************************************************************/
static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
{
- opcode_t *opc, *start, *end;
+ opcode_t *opc;
fill_new_table(env->opcodes, 0x40);
- if (&opc_start < &opc_end) {
- start = &opc_start;
- end = &opc_end;
- } else {
- start = &opc_end;
- end = &opc_start;
- }
- for (opc = start + 1; opc != end; opc++) {
- if ((opc->handler.type & def->insns_flags) != 0) {
+ for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
+ if (((opc->handler.type & def->insns_flags) != 0) ||
+ ((opc->handler.type2 & def->insns_flags2) != 0)) {
if (register_insn(env->opcodes, opc) < 0) {
printf("*** ERROR initializing PowerPC instruction "
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
static void dump_ppc_insns (CPUPPCState *env)
{
opc_handler_t **table, *handler;
- const unsigned char *p, *q;
+ const char *p, *q;
uint8_t opc1, opc2, opc3;
printf("Instructions set:\n");
}
#endif
+static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ stfq_p(mem_buf, env->fpr[n]);
+ return 8;
+ }
+ if (n == 32) {
+ /* FPSCR not implemented */
+ memset(mem_buf, 0, 4);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ env->fpr[n] = ldfq_p(mem_buf);
+ return 8;
+ }
+ if (n == 32) {
+ /* FPSCR not implemented */
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+#ifdef HOST_WORDS_BIGENDIAN
+ stq_p(mem_buf, env->avr[n].u64[0]);
+ stq_p(mem_buf+8, env->avr[n].u64[1]);
+#else
+ stq_p(mem_buf, env->avr[n].u64[1]);
+ stq_p(mem_buf+8, env->avr[n].u64[0]);
+#endif
+ return 16;
+ }
+ if (n == 32) {
+ stl_p(mem_buf, env->vscr);
+ return 4;
+ }
+ if (n == 33) {
+ stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+#ifdef HOST_WORDS_BIGENDIAN
+ env->avr[n].u64[0] = ldq_p(mem_buf);
+ env->avr[n].u64[1] = ldq_p(mem_buf+8);
+#else
+ env->avr[n].u64[1] = ldq_p(mem_buf);
+ env->avr[n].u64[0] = ldq_p(mem_buf+8);
+#endif
+ return 16;
+ }
+ if (n == 32) {
+ env->vscr = ldl_p(mem_buf);
+ return 4;
+ }
+ if (n == 33) {
+ env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+#if defined(TARGET_PPC64)
+ stl_p(mem_buf, env->gpr[n] >> 32);
+#else
+ stl_p(mem_buf, env->gprh[n]);
+#endif
+ return 4;
+ }
+ if (n == 32) {
+ stq_p(mem_buf, env->spe_acc);
+ return 8;
+ }
+ if (n == 33) {
+ stl_p(mem_buf, env->spe_fscr);
+ return 4;
+ }
+ return 0;
+}
+
+static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+#if defined(TARGET_PPC64)
+ target_ulong lo = (uint32_t)env->gpr[n];
+ target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
+ env->gpr[n] = lo | hi;
+#else
+ env->gprh[n] = ldl_p(mem_buf);
+#endif
+ return 4;
+ }
+ if (n == 32) {
+ env->spe_acc = ldq_p(mem_buf);
+ return 8;
+ }
+ if (n == 33) {
+ env->spe_fscr = ldl_p(mem_buf);
+ return 4;
+ }
+ return 0;
+}
+
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
{
env->msr_mask = def->msr_mask;
env->mmu_model = def->mmu_model;
env->excp_model = def->excp_model;
env->bus_model = def->bus_model;
+ env->insns_flags = def->insns_flags;
+ env->insns_flags2 = def->insns_flags2;
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
if (create_ppc_opcodes(env, def) < 0)
return -1;
init_ppc_proc(env, def);
+
+ if (def->insns_flags & PPC_FLOAT) {
+ gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
+ 33, "power-fpu.xml", 0);
+ }
+ if (def->insns_flags & PPC_ALTIVEC) {
+ gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
+ 34, "power-altivec.xml", 0);
+ }
+ if (def->insns_flags & PPC_SPE) {
+ gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
+ 34, "power-spe.xml", 0);
+ }
+
#if defined(PPC_DUMP_CPU)
{
- const unsigned char *mmu_model, *excp_model, *bus_model;
+ const char *mmu_model, *excp_model, *bus_model;
switch (env->mmu_model) {
case POWERPC_MMU_32B:
mmu_model = "PowerPC 32";
case POWERPC_MMU_BOOKE:
mmu_model = "PowerPC BookE";
break;
- case POWERPC_MMU_BOOKE_FSL:
- mmu_model = "PowerPC BookE FSL";
+ case POWERPC_MMU_BOOKE206:
+ mmu_model = "PowerPC BookE 2.06";
break;
case POWERPC_MMU_601:
mmu_model = "PowerPC 601";
case POWERPC_MMU_64B:
mmu_model = "PowerPC 64";
break;
+ case POWERPC_MMU_620:
+ mmu_model = "PowerPC 620";
+ break;
#endif
default:
mmu_model = "Unknown or invalid";
int i, best, match, best_match, max;
ret = NULL;
- max = sizeof(ppc_defs) / sizeof(ppc_def_t);
+ max = ARRAY_SIZE(ppc_defs);
best = -1;
pvr_rev = pvr & 0xFFFF;
/* We want all specified bits to match */
#include <ctype.h>
-const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
+const ppc_def_t *cpu_ppc_find_by_name (const char *name)
{
const ppc_def_t *ret;
- const unsigned char *p;
+ const char *p;
int i, max, len;
/* Check if the given name is a PVR */
p = name;
check_pvr:
for (i = 0; i < 8; i++) {
- if (!isxdigit(*p++))
+ if (!qemu_isxdigit(*p++))
break;
}
if (i == 8)
return ppc_find_by_pvr(strtoul(name, NULL, 16));
}
ret = NULL;
- max = sizeof(ppc_defs) / sizeof(ppc_def_t);
+ max = ARRAY_SIZE(ppc_defs);
for (i = 0; i < max; i++) {
if (strcasecmp(name, ppc_defs[i].name) == 0) {
ret = &ppc_defs[i];
return ret;
}
-void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
+void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
{
int i, max;
- max = sizeof(ppc_defs) / sizeof(ppc_def_t);
+ max = ARRAY_SIZE(ppc_defs);
for (i = 0; i < max; i++) {
(*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
ppc_defs[i].name, ppc_defs[i].pvr);
projects / qemu.git / blobdiff