configure: Copy test data to build directory

[qemu.git] / target-sh4 / translate.c

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 04bc94a0b1a446ffa5ed15531b6f5d9b475c53e2..569bc738cb26a8e2bbfeb21dc009b4a4fa939a81 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -27,7 +27,6 @@
 //#define SH4_SINGLE_STEP
 
 #include "cpu.h"
-#include "exec-all.h"
 #include "disas.h"
 #include "tcg-op.h"
 #include "qemu-common.h"
@@ -302,7 +301,7 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
        /* Use a direct jump if in same page and singlestep not enabled */
         tcg_gen_goto_tb(n);
         tcg_gen_movi_i32(cpu_pc, dest);
-        tcg_gen_exit_tb((long) tb + n);
+        tcg_gen_exit_tb((tcg_target_long)tb + n);
     } else {
         tcg_gen_movi_i32(cpu_pc, dest);
         if (ctx->singlestep_enabled)
@@ -332,7 +331,7 @@ static inline void gen_branch_slot(uint32_t delayed_pc, int t)
     tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
     sr = tcg_temp_new();
     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
-    tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
+    tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label);
     tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
     gen_set_label(label);
 }
@@ -347,7 +346,7 @@ static void gen_conditional_jump(DisasContext * ctx,
     l1 = gen_new_label();
     sr = tcg_temp_new();
     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
-    tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
+    tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1);
     gen_goto_tb(ctx, 0, ifnott);
     gen_set_label(l1);
     gen_goto_tb(ctx, 1, ift);
@@ -362,7 +361,7 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
     l1 = gen_new_label();
     ds = tcg_temp_new();
     tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
-    tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
+    tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
     gen_goto_tb(ctx, 1, ctx->pc + 2);
     gen_set_label(l1);
     tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
@@ -381,26 +380,26 @@ static inline void gen_clr_t(void)
 
 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
 {
-    int label1 = gen_new_label();
-    int label2 = gen_new_label();
-    tcg_gen_brcond_i32(cond, t1, t0, label1);
-    gen_clr_t();
-    tcg_gen_br(label2);
-    gen_set_label(label1);
-    gen_set_t();
-    gen_set_label(label2);
+    TCGv t;
+
+    t = tcg_temp_new();
+    tcg_gen_setcond_i32(cond, t, t1, t0);
+    tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+    tcg_gen_or_i32(cpu_sr, cpu_sr, t);
+
+    tcg_temp_free(t);
 }
 
 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
 {
-    int label1 = gen_new_label();
-    int label2 = gen_new_label();
-    tcg_gen_brcondi_i32(cond, t0, imm, label1);
-    gen_clr_t();
-    tcg_gen_br(label2);
-    gen_set_label(label1);
-    gen_set_t();
-    gen_set_label(label2);
+    TCGv t;
+
+    t = tcg_temp_new();
+    tcg_gen_setcondi_i32(cond, t, t0, imm);
+    tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+    tcg_gen_or_i32(cpu_sr, cpu_sr, t);
+
+    tcg_temp_free(t);
 }
 
 static inline void gen_store_flags(uint32_t flags)
@@ -816,24 +815,22 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0x200c:               /* cmp/str Rm,Rn */
        {
-           int label1 = gen_new_label();
-           int label2 = gen_new_label();
-           TCGv cmp1 = tcg_temp_local_new();
-           TCGv cmp2 = tcg_temp_local_new();
+           TCGv cmp1 = tcg_temp_new();
+           TCGv cmp2 = tcg_temp_new();
+           tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
            tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
            tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
-           tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+           tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+           tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
            tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
-           tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+           tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+           tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
            tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
-           tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+           tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+           tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
            tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
-           tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
-           tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
-           tcg_gen_br(label2);
-           gen_set_label(label1);
-           tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
-           gen_set_label(label2);
+           tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+           tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
            tcg_temp_free(cmp2);
            tcg_temp_free(cmp1);
        }
@@ -954,7 +951,21 @@ static void _decode_opc(DisasContext * ctx)
        tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
        return;
     case 0x600a:               /* negc Rm,Rn */
-       gen_helper_negc(REG(B11_8), REG(B7_4));
+        {
+           TCGv t0, t1;
+            t0 = tcg_temp_new();
+            tcg_gen_neg_i32(t0, REG(B7_4));
+            t1 = tcg_temp_new();
+            tcg_gen_andi_i32(t1, cpu_sr, SR_T);
+            tcg_gen_sub_i32(REG(B11_8), t0, t1);
+            tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+            tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_temp_free(t0);
+            tcg_temp_free(t1);
+        }
        return;
     case 0x6007:               /* not Rm,Rn */
        tcg_gen_not_i32(REG(B11_8), REG(B7_4));
@@ -1692,14 +1703,12 @@ static void _decode_opc(DisasContext * ctx)
        }
        return;
     case 0x4004:               /* rotl Rn */
-       gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
-       tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
-       gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
+       tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1);
+       gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
        return;
     case 0x4005:               /* rotr Rn */
        gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
-       tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
-       gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
+       tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1);
        return;
     case 0x4000:               /* shll Rn */
     case 0x4020:               /* shal Rn */
@@ -1892,6 +1901,10 @@ static void decode_opc(DisasContext * ctx)
 {
     uint32_t old_flags = ctx->flags;
 
+    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+        tcg_gen_debug_insn_start(ctx->pc);
+    }
+
     _decode_opc(ctx);
 
     if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
@@ -2055,8 +2068,7 @@ void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
     gen_intermediate_code_internal(env, tb, 1);
 }
 
-void gen_pc_load(CPUState *env, TranslationBlock *tb,
-                unsigned long searched_pc, int pc_pos, void *puc)
+void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
 {
     env->pc = gen_opc_pc[pc_pos];
     env->flags = gen_opc_hflags[pc_pos];