* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
-#include <assert.h>
#define DEBUG_DISAS
#define SH4_DEBUG_DISAS
//#define SH4_SINGLE_STEP
#include "cpu.h"
-#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-common.h"
int memidx;
uint32_t delayed_pc;
int singlestep_enabled;
+ uint32_t features;
+ int has_movcal;
} DisasContext;
#if defined(CONFIG_USER_ONLY)
static TCGv cpu_gregs[24];
static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
-static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
+static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
+static TCGv cpu_fregs[32];
/* internal register indexes */
static TCGv cpu_flags, cpu_delayed_pc;
+static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
+
#include "gen-icount.h"
static void sh4_translate_init(void)
"R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
};
+ static const char * const fregnames[32] = {
+ "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
+ "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
+ "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
+ "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
+ "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
+ "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
+ "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
+ "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
+ };
if (done_init)
return;
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, gregs[i]),
- gregnames[i]);
+ offsetof(CPUState, gregs[i]),
+ gregnames[i]);
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, pc), "PC");
cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUState, delayed_pc),
"_delayed_pc_");
+ cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, ldst), "_ldst_");
+
+ for (i = 0; i < 32; i++)
+ cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, fregs[i]),
+ fregnames[i]);
/* register helpers */
#define GEN_HELPER 2
}
}
-void cpu_sh4_reset(CPUSH4State * env)
+void cpu_reset(CPUSH4State * env)
{
-#if defined(CONFIG_USER_ONLY)
- env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
-#else
- env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */
-#endif
- env->vbr = 0;
+ if (qemu_loglevel_mask(CPU_LOG_RESET)) {
+ qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
+ log_cpu_state(env, 0);
+ }
+
+ memset(env, 0, offsetof(CPUSH4State, breakpoints));
+ tlb_flush(env, 1);
+
env->pc = 0xA0000000;
#if defined(CONFIG_USER_ONLY)
env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
#else
- env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
+ env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
+ env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+ set_flush_to_zero(1, &env->fp_status);
#endif
- env->mmucr = 0;
+ set_default_nan_mode(1, &env->fp_status);
}
typedef struct {
uint32_t pvr;
uint32_t prr;
uint32_t cvr;
+ uint32_t features;
} sh4_def_t;
static sh4_def_t sh4_defs[] = {
.pvr = 0x00050000,
.prr = 0x00000100,
.cvr = 0x00110000,
+ .features = SH_FEATURE_BCR3_AND_BCR4,
}, {
.name = "SH7751R",
.id = SH_CPU_SH7751R,
.pvr = 0x04050005,
.prr = 0x00000113,
.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
- },
+ .features = SH_FEATURE_BCR3_AND_BCR4,
+ }, {
+ .name = "SH7785",
+ .id = SH_CPU_SH7785,
+ .pvr = 0x10300700,
+ .prr = 0x00000200,
+ .cvr = 0x71440211,
+ .features = SH_FEATURE_SH4A,
+ },
};
static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
if (strcasecmp(name, "any") == 0)
return &sh4_defs[0];
- for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
+ for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
if (strcasecmp(name, sh4_defs[i].name) == 0)
return &sh4_defs[i];
return NULL;
}
-void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
int i;
- for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
+ for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
(*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
}
-static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
+static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
{
env->pvr = def->pvr;
env->prr = def->prr;
if (!def)
return NULL;
env = qemu_mallocz(sizeof(CPUSH4State));
- if (!env)
- return NULL;
+ env->features = def->features;
cpu_exec_init(env);
+ env->movcal_backup_tail = &(env->movcal_backup);
sh4_translate_init();
env->cpu_model_str = cpu_model;
- cpu_sh4_reset(env);
- cpu_sh4_register(env, def);
- tlb_flush(env, 1);
+ cpu_reset(env);
+ cpu_register(env, def);
+ qemu_init_vcpu(env);
return env;
}
/* Use a direct jump if in same page and singlestep not enabled */
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb((long) tb + n);
+ tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
if (ctx->singlestep_enabled)
tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
sr = tcg_temp_new();
tcg_gen_andi_i32(sr, cpu_sr, SR_T);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
+ tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label);
tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
gen_set_label(label);
}
l1 = gen_new_label();
sr = tcg_temp_new();
tcg_gen_andi_i32(sr, cpu_sr, SR_T);
- tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1);
gen_goto_tb(ctx, 0, ifnott);
gen_set_label(l1);
gen_goto_tb(ctx, 1, ift);
l1 = gen_new_label();
ds = tcg_temp_new();
tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
- tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
gen_goto_tb(ctx, 1, ctx->pc + 2);
gen_set_label(l1);
tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
- tcg_gen_brcond_i32(cond, t1, t0, label1);
- gen_clr_t();
- tcg_gen_br(label2);
- gen_set_label(label1);
- gen_set_t();
- gen_set_label(label2);
+ TCGv t;
+
+ t = tcg_temp_new();
+ tcg_gen_setcond_i32(cond, t, t1, t0);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t);
+
+ tcg_temp_free(t);
}
static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
- tcg_gen_brcondi_i32(cond, t0, imm, label1);
- gen_clr_t();
- tcg_gen_br(label2);
- gen_set_label(label1);
- gen_set_t();
- gen_set_label(label2);
+ TCGv t;
+
+ t = tcg_temp_new();
+ tcg_gen_setcondi_i32(cond, t, t0, imm);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t);
+
+ tcg_temp_free(t);
}
static inline void gen_store_flags(uint32_t flags)
tcg_temp_free(tmp);
}
-
-static inline void gen_load_fpr32(TCGv_i32 t, int reg)
-{
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
-}
-
static inline void gen_load_fpr64(TCGv_i64 t, int reg)
{
- TCGv_i32 tmp1 = tcg_temp_new_i32();
- TCGv_i32 tmp2 = tcg_temp_new_i32();
-
- tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
- tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
- tcg_gen_concat_i32_i64(t, tmp2, tmp1);
- tcg_temp_free_i32(tmp1);
- tcg_temp_free_i32(tmp2);
-}
-
-static inline void gen_store_fpr32(TCGv_i32 t, int reg)
-{
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
+ tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
}
static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
{
TCGv_i32 tmp = tcg_temp_new_i32();
-
tcg_gen_trunc_i64_i32(tmp, t);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
+ tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
tcg_gen_shri_i64(t, t, 32);
tcg_gen_trunc_i64_i32(tmp, t);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
+ tcg_gen_mov_i32(cpu_fregs[reg], tmp);
tcg_temp_free_i32(tmp);
}
#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
#define CHECK_NOT_DELAY_SLOT \
- if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
- {gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \
- return;}
-
-#define CHECK_PRIVILEGED \
- if (IS_USER(ctx)) { \
- gen_helper_raise_illegal_instruction(); \
+ if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
+ { \
+ gen_helper_raise_slot_illegal_instruction(); \
ctx->bstate = BS_EXCP; \
return; \
}
+#define CHECK_PRIVILEGED \
+ if (IS_USER(ctx)) { \
+ if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
+ gen_helper_raise_slot_illegal_instruction(); \
+ } else { \
+ gen_helper_raise_illegal_instruction(); \
+ } \
+ ctx->bstate = BS_EXCP; \
+ return; \
+ }
+
+#define CHECK_FPU_ENABLED \
+ if (ctx->flags & SR_FD) { \
+ if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
+ gen_helper_raise_slot_fpu_disable(); \
+ } else { \
+ gen_helper_raise_fpu_disable(); \
+ } \
+ ctx->bstate = BS_EXCP; \
+ return; \
+ }
+
static void _decode_opc(DisasContext * ctx)
{
+ /* This code tries to make movcal emulation sufficiently
+ accurate for Linux purposes. This instruction writes
+ memory, and prior to that, always allocates a cache line.
+ It is used in two contexts:
+ - in memcpy, where data is copied in blocks, the first write
+ of to a block uses movca.l for performance.
+ - in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
+ to flush the cache. Here, the data written by movcal.l is never
+ written to memory, and the data written is just bogus.
+
+ To simulate this, we simulate movcal.l, we store the value to memory,
+ but we also remember the previous content. If we see ocbi, we check
+ if movcal.l for that address was done previously. If so, the write should
+ not have hit the memory, so we restore the previous content.
+ When we see an instruction that is neither movca.l
+ nor ocbi, the previous content is discarded.
+
+ To optimize, we only try to flush stores when we're at the start of
+ TB, or if we already saw movca.l in this TB and did not flush stores
+ yet. */
+ if (ctx->has_movcal)
+ {
+ int opcode = ctx->opcode & 0xf0ff;
+ if (opcode != 0x0093 /* ocbi */
+ && opcode != 0x00c3 /* movca.l */)
+ {
+ gen_helper_discard_movcal_backup ();
+ ctx->has_movcal = 0;
+ }
+ }
+
#if 0
fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
#endif
+
switch (ctx->opcode) {
case 0x0019: /* div0u */
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 1);
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
+ tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
tcg_temp_free(addr);
}
return;
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
return;
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
+ tcg_gen_mov_i32(REG(B11_8), addr);
}
return;
case 0x6004: /* mov.b @Rm+,Rn */
return;
case 0x6008: /* swap.b Rm,Rn */
{
- TCGv highw, high, low;
- highw = tcg_temp_new();
- tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
+ TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext8u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 8);
+ tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000);
low = tcg_temp_new();
- tcg_gen_shri_i32(low, REG(B7_4), 8);
- tcg_gen_ext8u_i32(low, low);
+ tcg_gen_ext16u_i32(low, REG(B7_4));
+ tcg_gen_bswap16_i32(low, low);
tcg_gen_or_i32(REG(B11_8), high, low);
- tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
tcg_temp_free(low);
tcg_temp_free(high);
}
{
TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext16u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 16);
+ tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B7_4), 16);
tcg_gen_ext16u_i32(low, low);
{
TCGv high, low;
high = tcg_temp_new();
- tcg_gen_ext16u_i32(high, REG(B7_4));
- tcg_gen_shli_i32(high, high, 16);
+ tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B11_8), 16);
tcg_gen_ext16u_i32(low, low);
return;
case 0x200c: /* cmp/str Rm,Rn */
{
- int label1 = gen_new_label();
- int label2 = gen_new_label();
- TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32);
- TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv cmp1 = tcg_temp_new();
+ TCGv cmp2 = tcg_temp_new();
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
- tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
- tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
- tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
- tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
- tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
- tcg_gen_br(label2);
- gen_set_label(label1);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
- gen_set_label(label2);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
tcg_temp_free(cmp2);
tcg_temp_free(cmp1);
}
tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
return;
case 0x600a: /* negc Rm,Rn */
- gen_helper_negc(REG(B11_8), REG(B7_4));
+ {
+ TCGv t0, t1;
+ t0 = tcg_temp_new();
+ tcg_gen_neg_i32(t0, REG(B7_4));
+ t1 = tcg_temp_new();
+ tcg_gen_andi_i32(t1, cpu_sr, SR_T);
+ tcg_gen_sub_i32(REG(B11_8), t0, t1);
+ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+ tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0);
+ tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
return;
case 0x6007: /* not Rm,Rn */
tcg_gen_not_i32(REG(B11_8), REG(B7_4));
int label2 = gen_new_label();
int label3 = gen_new_label();
int label4 = gen_new_label();
- TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label4);
/* Rm negative, shift to the right */
gen_set_label(label1);
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
tcg_gen_not_i32(shift, REG(B7_4));
tcg_gen_andi_i32(shift, shift, 0x1f);
tcg_gen_addi_i32(shift, shift, 1);
tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label4);
/* Rm = -32 */
gen_set_label(label2);
gen_set_label(label3);
tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
gen_set_label(label4);
- tcg_temp_free(shift);
}
return;
case 0x400d: /* shld Rm,Rn */
int label1 = gen_new_label();
int label2 = gen_new_label();
int label3 = gen_new_label();
- TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv shift;
tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
/* Rm positive, shift to the left */
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label3);
/* Rm negative, shift to the right */
gen_set_label(label1);
+ shift = tcg_temp_new();
tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
tcg_gen_not_i32(shift, REG(B7_4));
tcg_gen_andi_i32(shift, shift, 0x1f);
tcg_gen_addi_i32(shift, shift, 1);
tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
+ tcg_temp_free(shift);
tcg_gen_br(label3);
/* Rm = -32 */
gen_set_label(label2);
tcg_gen_movi_i32(REG(B11_8), 0);
gen_set_label(label3);
- tcg_temp_free(shift);
}
return;
case 0x3008: /* sub Rm,Rn */
tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, XREG(B7_4));
gen_store_fpr64(fp, XREG(B11_8));
tcg_temp_free_i64(fp);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B7_4));
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
}
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B7_4);
+ tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B7_4));
- tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_temp_free(addr_hi);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
- tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
+ TCGv addr_hi = tcg_temp_new();
+ int fr = XREG(B11_8);
+ tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
+ tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
+ tcg_temp_free(addr_hi);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
}
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_SZ) {
- TCGv addr;
- TCGv_i64 fp;
- addr = tcg_temp_new();
- tcg_gen_subi_i32(addr, REG(B11_8), 8);
- fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ TCGv addr = tcg_temp_new_i32();
+ int fr = XREG(B7_4);
+ tcg_gen_subi_i32(addr, REG(B11_8), 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
+ tcg_gen_subi_i32(addr, addr, 4);
+ tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
} else {
TCGv addr;
- TCGv_i32 fp;
addr = tcg_temp_new_i32();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
- fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B7_4));
- tcg_gen_qemu_st32(fp, addr, ctx->memidx);
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
{
TCGv addr = tcg_temp_new_i32();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
- gen_store_fpr64(fp, XREG(B11_8));
- tcg_temp_free_i64(fp);
+ int fr = XREG(B11_8);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
}
tcg_temp_free(addr);
}
return;
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
if (ctx->fpscr & FPSCR_SZ) {
- TCGv_i64 fp = tcg_temp_new_i64();
- gen_load_fpr64(fp, XREG(B7_4));
- tcg_gen_qemu_st64(fp, addr, ctx->memidx);
- tcg_temp_free_i64(fp);
+ int fr = XREG(B7_4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
+ tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B7_4));
- tcg_gen_qemu_st32(fp, addr, ctx->memidx);
- tcg_temp_free_i32(fp);
+ tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
}
tcg_temp_free(addr);
}
case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
{
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_PR) {
TCGv_i64 fp0, fp1;
tcg_temp_free_i64(fp0);
tcg_temp_free_i64(fp1);
} else {
- TCGv_i32 fp0, fp1;
-
- fp0 = tcg_temp_new_i32();
- fp1 = tcg_temp_new_i32();
- gen_load_fpr32(fp0, FREG(B11_8));
- gen_load_fpr32(fp1, FREG(B7_4));
-
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
- gen_helper_fadd_FT(fp0, fp0, fp1);
+ gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
break;
case 0xf001: /* fsub Rm,Rn */
- gen_helper_fsub_FT(fp0, fp0, fp1);
+ gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
break;
case 0xf002: /* fmul Rm,Rn */
- gen_helper_fmul_FT(fp0, fp0, fp1);
+ gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
break;
case 0xf003: /* fdiv Rm,Rn */
- gen_helper_fdiv_FT(fp0, fp0, fp1);
+ gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
break;
case 0xf004: /* fcmp/eq Rm,Rn */
- gen_helper_fcmp_eq_FT(fp0, fp1);
+ gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
return;
case 0xf005: /* fcmp/gt Rm,Rn */
- gen_helper_fcmp_gt_FT(fp0, fp1);
+ gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
return;
}
- gen_store_fpr32(fp0, FREG(B11_8));
- tcg_temp_free_i32(fp0);
- tcg_temp_free_i32(fp1);
}
}
return;
+ case 0xf00e: /* fmac FR0,RM,Rn */
+ {
+ CHECK_FPU_ENABLED
+ if (ctx->fpscr & FPSCR_PR) {
+ break; /* illegal instruction */
+ } else {
+ gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
+ cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
+ return;
+ }
+ }
}
switch (ctx->opcode & 0xff00) {
{
TCGv imm;
CHECK_NOT_DELAY_SLOT
- tcg_gen_movi_i32(cpu_pc, ctx->pc);
imm = tcg_const_i32(B7_0);
gen_helper_trapa(imm);
tcg_temp_free(imm);
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
}
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
-#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
+#define LD(reg,ldnum,ldpnum,prechk) \
case ldnum: \
prechk \
tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
prechk \
tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
- return; \
+ return;
+#define ST(reg,stnum,stpnum,prechk) \
case stnum: \
prechk \
tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
case stpnum: \
prechk \
{ \
- TCGv addr = tcg_temp_new(); \
+ TCGv addr = tcg_temp_new(); \
tcg_gen_subi_i32(addr, REG(B11_8), 4); \
tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
+ tcg_gen_mov_i32(REG(B11_8), addr); \
tcg_temp_free(addr); \
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
} \
return;
+#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
+ LD(reg,ldnum,ldpnum,prechk) \
+ ST(reg,stnum,stpnum,prechk)
LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
+ ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED)
+ LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;)
LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {})
- LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {})
+ LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
case 0x406a: /* lds Rm,FPSCR */
+ CHECK_FPU_ENABLED
gen_helper_ld_fpscr(REG(B11_8));
ctx->bstate = BS_STOP;
return;
case 0x4066: /* lds.l @Rm+,FPSCR */
+ CHECK_FPU_ENABLED
{
TCGv addr = tcg_temp_new();
tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
}
return;
case 0x006a: /* sts FPSCR,Rn */
+ CHECK_FPU_ENABLED
tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
return;
case 0x4062: /* sts FPSCR,@-Rn */
+ CHECK_FPU_ENABLED
{
TCGv addr, val;
val = tcg_temp_new();
addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st32(val, addr, ctx->memidx);
+ tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
tcg_temp_free(val);
- tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
case 0x00c3: /* movca.l R0,@Rm */
- tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
+ {
+ TCGv val = tcg_temp_new();
+ tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
+ gen_helper_movcal (REG(B11_8), val);
+ tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
+ }
+ ctx->has_movcal = 1;
return;
case 0x40a9:
/* MOVUA.L @Rm,R0 (Rm) -> R0
case 0x0029: /* movt Rn */
tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
return;
+ case 0x0073:
+ /* MOVCO.L
+ LDST -> T
+ If (T == 1) R0 -> (Rn)
+ 0 -> LDST
+ */
+ if (ctx->features & SH_FEATURE_SH4A) {
+ int label = gen_new_label();
+ gen_clr_t();
+ tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
+ tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
+ gen_set_label(label);
+ tcg_gen_movi_i32(cpu_ldst, 0);
+ return;
+ } else
+ break;
+ case 0x0063:
+ /* MOVLI.L @Rm,R0
+ 1 -> LDST
+ (Rm) -> R0
+ When interrupt/exception
+ occurred 0 -> LDST
+ */
+ if (ctx->features & SH_FEATURE_SH4A) {
+ tcg_gen_movi_i32(cpu_ldst, 0);
+ tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
+ tcg_gen_movi_i32(cpu_ldst, 1);
+ return;
+ } else
+ break;
case 0x0093: /* ocbi @Rn */
{
- TCGv dummy = tcg_temp_new();
- tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
- tcg_temp_free(dummy);
+ gen_helper_ocbi (REG(B11_8));
}
return;
case 0x00a3: /* ocbp @Rn */
return;
case 0x0083: /* pref @Rn */
return;
+ case 0x00d3: /* prefi @Rn */
+ if (ctx->features & SH_FEATURE_SH4A)
+ return;
+ else
+ break;
+ case 0x00e3: /* icbi @Rn */
+ if (ctx->features & SH_FEATURE_SH4A)
+ return;
+ else
+ break;
+ case 0x00ab: /* synco */
+ if (ctx->features & SH_FEATURE_SH4A)
+ return;
+ else
+ break;
case 0x4024: /* rotcl Rn */
{
TCGv tmp = tcg_temp_new();
}
return;
case 0x4004: /* rotl Rn */
- gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
- tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
- gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
+ tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1);
+ gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
return;
case 0x4005: /* rotr Rn */
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
- tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
- gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
+ tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1);
return;
case 0x4000: /* shll Rn */
case 0x4020: /* shal Rn */
case 0x401b: /* tas.b @Rn */
{
TCGv addr, val;
- addr = tcg_temp_local_new(TCG_TYPE_I32);
+ addr = tcg_temp_local_new();
tcg_gen_mov_i32(addr, REG(B11_8));
- val = tcg_temp_local_new(TCG_TYPE_I32);
+ val = tcg_temp_local_new();
tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
gen_cmp_imm(TCG_COND_EQ, val, 0);
tcg_gen_ori_i32(val, val, 0x80);
}
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
- {
- TCGv fp = tcg_temp_new();
- tcg_gen_mov_i32(fp, cpu_fpul);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free(fp);
- }
+ CHECK_FPU_ENABLED
+ tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
return;
case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
- {
- TCGv fp = tcg_temp_new();
- gen_load_fpr32(fp, FREG(B11_8));
- tcg_gen_mov_i32(cpu_fpul, fp);
- tcg_temp_free(fp);
- }
+ CHECK_FPU_ENABLED
+ tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
return;
case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_PR) {
TCGv_i64 fp;
if (ctx->opcode & 0x0100)
tcg_temp_free_i64(fp);
}
else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_helper_float_FT(fp, cpu_fpul);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
}
return;
case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_PR) {
TCGv_i64 fp;
if (ctx->opcode & 0x0100)
tcg_temp_free_i64(fp);
}
else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B11_8));
- gen_helper_ftrc_FT(cpu_fpul, fp);
- tcg_temp_free_i32(fp);
+ gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
+ CHECK_FPU_ENABLED
{
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B11_8));
- gen_helper_fneg_T(fp, fp);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf05d: /* fabs FRn/DRn */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B11_8));
- gen_helper_fabs_FT(fp, fp);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf06d: /* fsqrt FRn */
+ CHECK_FPU_ENABLED
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
- TCGv_i32 fp = tcg_temp_new_i32();
- gen_load_fpr32(fp, FREG(B11_8));
- gen_helper_fsqrt_FT(fp, fp);
- gen_store_fpr32(fp, FREG(B11_8));
- tcg_temp_free_i32(fp);
+ gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
}
return;
case 0xf07d: /* fsrra FRn */
+ CHECK_FPU_ENABLED
break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
+ CHECK_FPU_ENABLED
if (!(ctx->fpscr & FPSCR_PR)) {
- TCGv_i32 val = tcg_const_i32(0);
- gen_load_fpr32(val, FREG(B11_8));
- tcg_temp_free_i32(val);
- return;
+ tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
}
- break;
+ return;
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
+ CHECK_FPU_ENABLED
if (!(ctx->fpscr & FPSCR_PR)) {
- TCGv_i32 val = tcg_const_i32(0x3f800000);
- gen_load_fpr32(val, FREG(B11_8));
- tcg_temp_free_i32(val);
- return;
+ tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
}
- break;
+ return;
case 0xf0ad: /* fcnvsd FPUL,DRn */
+ CHECK_FPU_ENABLED
{
TCGv_i64 fp = tcg_temp_new_i64();
gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
}
return;
case 0xf0bd: /* fcnvds DRn,FPUL */
+ CHECK_FPU_ENABLED
{
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
}
return;
+ case 0xf0ed: /* fipr FVm,FVn */
+ CHECK_FPU_ENABLED
+ if ((ctx->fpscr & FPSCR_PR) == 0) {
+ TCGv m, n;
+ m = tcg_const_i32((ctx->opcode >> 16) & 3);
+ n = tcg_const_i32((ctx->opcode >> 18) & 3);
+ gen_helper_fipr(m, n);
+ tcg_temp_free(m);
+ tcg_temp_free(n);
+ return;
+ }
+ break;
+ case 0xf0fd: /* ftrv XMTRX,FVn */
+ CHECK_FPU_ENABLED
+ if ((ctx->opcode & 0x0300) == 0x0100 &&
+ (ctx->fpscr & FPSCR_PR) == 0) {
+ TCGv n;
+ n = tcg_const_i32((ctx->opcode >> 18) & 3);
+ gen_helper_ftrv(n);
+ tcg_temp_free(n);
+ return;
+ }
+ break;
}
-
+#if 0
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
ctx->opcode, ctx->pc);
- gen_helper_raise_illegal_instruction();
+ fflush(stderr);
+#endif
+ if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
+ gen_helper_raise_slot_illegal_instruction();
+ } else {
+ gen_helper_raise_illegal_instruction();
+ }
ctx->bstate = BS_EXCP;
}
{
uint32_t old_flags = ctx->flags;
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(ctx->pc);
+ }
+
_decode_opc(ctx);
if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
DisasContext ctx;
target_ulong pc_start;
static uint16_t *gen_opc_end;
+ CPUBreakpoint *bp;
int i, ii;
int num_insns;
int max_insns;
ctx.bstate = BS_NONE;
ctx.sr = env->sr;
ctx.fpscr = env->fpscr;
- ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
+ ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
/* We don't know if the delayed pc came from a dynamic or static branch,
so assume it is a dynamic branch. */
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb;
ctx.singlestep_enabled = env->singlestep_enabled;
-
-#ifdef DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_CPU) {
- fprintf(logfile,
- "------------------------------------------------\n");
- cpu_dump_state(env, logfile, fprintf, 0);
- }
-#endif
+ ctx.features = env->features;
+ ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
ii = -1;
num_insns = 0;
max_insns = CF_COUNT_MASK;
gen_icount_start();
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
- if (env->nb_breakpoints > 0) {
- for (i = 0; i < env->nb_breakpoints; i++) {
- if (ctx.pc == env->breakpoints[i]) {
+ if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
+ QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (ctx.pc == bp->pc) {
/* We have hit a breakpoint - make sure PC is up-to-date */
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug();
break;
if (num_insns >= max_insns)
break;
-#ifdef SH4_SINGLE_STEP
- break;
-#endif
+ if (singlestep)
+ break;
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
#ifdef DEBUG_DISAS
#ifdef SH4_DEBUG_DISAS
- if (loglevel & CPU_LOG_TB_IN_ASM)
- fprintf(logfile, "\n");
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
#endif
- if (loglevel & CPU_LOG_TB_IN_ASM) {
- fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */
- target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
- fprintf(logfile, "\n");
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
+ log_target_disas(pc_start, ctx.pc - pc_start, 0);
+ qemu_log("\n");
}
#endif
}
gen_intermediate_code_internal(env, tb, 1);
}
-void gen_pc_load(CPUState *env, TranslationBlock *tb,
- unsigned long searched_pc, int pc_pos, void *puc)
+void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
env->flags = gen_opc_hflags[pc_pos];
projects / qemu.git / blobdiff