static void raise_exception(int tt)
{
env->exception_index = tt;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void HELPER(raise_exception)(int tt)
/* Leon3 cache control */
-void leon3_cache_control_int(void)
+static void leon3_cache_control_int(void)
{
uint32_t state = 0;
DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
break;
};
- DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
+ DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
addr, ret, size);
return ret;
}
+void leon3_irq_manager(void *irq_manager, int intno)
+{
+ leon3_irq_ack(irq_manager, intno);
+ leon3_cache_control_int();
+}
+
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
{
uint64_t ret = 0;
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- ret = leon3_cache_control_ld(addr, size);
+ if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ ret = leon3_cache_control_ld(addr, size);
+ }
break;
case 0x01c00a00: /* MXCC control register */
if (size == 8)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
- case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
ret);
}
break;
+ case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ ret = env->mmubpctrv;
+ break;
+ case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ ret = env->mmubpctrc;
+ break;
+ case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ ret = env->mmubpctrs;
+ break;
+ case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+ ret = env->mmubpaction;
+ break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi, size);
case 0x00: /* Leon3 Cache Control */
case 0x08: /* Leon3 Instruction Cache config */
case 0x0C: /* Leon3 Date Cache config */
- leon3_cache_control_st(addr, val, size);
+ if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
+ leon3_cache_control_st(addr, val, size);
+ }
break;
case 0x01c00000: /* MXCC stream data register 0 */
// descriptor diagnostic
case 0x36: /* I-cache flash clear */
case 0x37: /* D-cache flash clear */
- case 0x4c: /* breakpoint action */
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
{
env->mmuregs[reg]);
}
break;
+ case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
+ env->mmubpctrv = val & 0xffffffff;
+ break;
+ case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
+ env->mmubpctrc = val & 0x3;
+ break;
+ case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
+ env->mmubpctrs = val & 0x3;
+ break;
+ case 0x4c: /* SuperSPARC MMU Breakpoint Action */
+ env->mmubpaction = val & 0x1fff;
+ break;
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#ifndef TARGET_SPARC64
}
#endif
-void helper_flush(target_ulong addr)
-{
- addr &= ~7;
- tb_invalidate_page_range(addr, addr + 8);
-}
-
#ifdef TARGET_SPARC64
#ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = {
void do_interrupt(CPUState *env)
{
int intno = env->exception_index;
- trap_state* tsptr;
+ trap_state *tsptr;
#ifdef DEBUG_PCALL
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
- if (intno < 0 || intno >= 0x180)
+ if (intno < 0 || intno >= 0x180) {
name = "Unknown";
- else if (intno >= 0x100)
+ } else if (intno >= 0x100) {
name = "Trap Instruction";
- else if (intno >= 0xc0)
+ } else if (intno >= 0xc0) {
name = "Window Fill";
- else if (intno >= 0x80)
+ } else if (intno >= 0x80) {
name = "Window Spill";
- else {
+ } else {
name = excp_names[intno];
- if (!name)
+ if (!name) {
name = "Unknown";
+ }
}
qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
qemu_log(" code=");
ptr = (uint8_t *)env->pc;
- for(i = 0; i < 16; i++) {
+ for (i = 0; i < 16; i++) {
qemu_log(" %02x", ldub(ptr + i));
}
qemu_log("\n");
env->tl++;
} else {
env->pstate |= PS_RED;
- if (env->tl < env->maxtl)
+ if (env->tl < env->maxtl) {
env->tl++;
+ }
}
tsptr = cpu_tsptr(env);
static int count;
const char *name;
- if (intno < 0 || intno >= 0x100)
+ if (intno < 0 || intno >= 0x100) {
name = "Unknown";
- else if (intno >= 0x80)
+ } else if (intno >= 0x80) {
name = "Trap Instruction";
- else {
+ } else {
name = excp_names[intno];
- if (!name)
+ if (!name) {
name = "Unknown";
+ }
}
qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
qemu_log(" code=");
ptr = (uint8_t *)env->pc;
- for(i = 0; i < 16; i++) {
+ for (i = 0; i < 16; i++) {
qemu_log(" %02x", ldub(ptr + i));
}
qemu_log("\n");
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
- cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
+ cpu_restore_state(tb, env, pc);
}
}
}
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (ret) {
cpu_restore_state2(retaddr);
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}