*/
#include "cpu.h"
-#include "exec-all.h"
-#include "gdbstub.h"
-#include "qemu-common.h"
-#include "host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
+#include "qemu/host-utils.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
-#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
- a1, a2, a3, a4, a5, a6) \
- { .targno = (no), .type = (typ), .group = (grp) },
+static struct XtensaConfigList *xtensa_cores;
-static void reset_mmu(CPUState *env);
+void xtensa_register_core(XtensaConfigList *node)
+{
+ node->next = xtensa_cores;
+ xtensa_cores = node;
+}
-void cpu_reset(CPUXtensaState *env)
+static uint32_t check_hw_breakpoints(CPUXtensaState *env)
{
- env->exception_taken = 0;
- env->pc = env->config->exception_vector[EXC_RESET];
- env->sregs[LITBASE] &= ~1;
- env->sregs[PS] = xtensa_option_enabled(env->config,
- XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
- env->sregs[VECBASE] = env->config->vecbase;
-
- env->pending_irq_level = 0;
- reset_mmu(env);
+ unsigned i;
+
+ for (i = 0; i < env->config->ndbreak; ++i) {
+ if (env->cpu_watchpoint[i] &&
+ env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
+ return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
+ }
+ }
+ return 0;
}
-static const XtensaConfig core_config[] = {
- {
- .name = "sample-xtensa-core",
- .options = -1 ^
- (XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_MMU)),
- .gdb_regmap = {
- .num_regs = 176,
- .num_core_regs = 117,
- .reg = {
-#include "gdb-config-sample-xtensa-core.c"
- }
- },
- .nareg = 64,
- .ndepc = 1,
- .excm_level = 16,
- .vecbase = 0x5fff8400,
- .exception_vector = {
- [EXC_RESET] = 0x5fff8000,
- [EXC_WINDOW_OVERFLOW4] = 0x5fff8400,
- [EXC_WINDOW_UNDERFLOW4] = 0x5fff8440,
- [EXC_WINDOW_OVERFLOW8] = 0x5fff8480,
- [EXC_WINDOW_UNDERFLOW8] = 0x5fff84c0,
- [EXC_WINDOW_OVERFLOW12] = 0x5fff8500,
- [EXC_WINDOW_UNDERFLOW12] = 0x5fff8540,
- [EXC_KERNEL] = 0x5fff861c,
- [EXC_USER] = 0x5fff863c,
- [EXC_DOUBLE] = 0x5fff865c,
- },
- .ninterrupt = 13,
- .nlevel = 6,
- .interrupt_vector = {
- 0,
- 0,
- 0x5fff857c,
- 0x5fff859c,
- 0x5fff85bc,
- 0x5fff85dc,
- 0x5fff85fc,
- },
- .level_mask = {
- [4] = 1,
- },
- .interrupt = {
- [0] = {
- .level = 4,
- .inttype = INTTYPE_TIMER,
- },
- },
- .nccompare = 1,
- .timerint = {
- [0] = 0,
- },
- .clock_freq_khz = 912000,
- }, {
- .name = "dc232b",
- .options = -1 ^
- (XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
- XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)),
- .gdb_regmap = {
- .num_regs = 120,
- .num_core_regs = 52,
- .reg = {
-#include "gdb-config-dc232b.c"
+static void breakpoint_handler(CPUXtensaState *env)
+{
+ if (env->watchpoint_hit) {
+ if (env->watchpoint_hit->flags & BP_CPU) {
+ uint32_t cause;
+
+ env->watchpoint_hit = NULL;
+ cause = check_hw_breakpoints(env);
+ if (cause) {
+ debug_exception_env(env, cause);
}
- },
- .nareg = 32,
- .ndepc = 1,
- .excm_level = 3,
- .vecbase = 0xd0000000,
- .exception_vector = {
- [EXC_RESET] = 0xfe000000,
- [EXC_WINDOW_OVERFLOW4] = 0xd0000000,
- [EXC_WINDOW_UNDERFLOW4] = 0xd0000040,
- [EXC_WINDOW_OVERFLOW8] = 0xd0000080,
- [EXC_WINDOW_UNDERFLOW8] = 0xd00000c0,
- [EXC_WINDOW_OVERFLOW12] = 0xd0000100,
- [EXC_WINDOW_UNDERFLOW12] = 0xd0000140,
- [EXC_KERNEL] = 0xd0000300,
- [EXC_USER] = 0xd0000340,
- [EXC_DOUBLE] = 0xd00003c0,
- },
- .ninterrupt = 22,
- .nlevel = 6,
- .interrupt_vector = {
- 0,
- 0,
- 0xd0000180,
- 0xd00001c0,
- 0xd0000200,
- 0xd0000240,
- 0xd0000280,
- 0xd00002c0,
- },
- .level_mask = {
- [1] = 0x1f80ff,
- [2] = 0x000100,
- [3] = 0x200e00,
- [4] = 0x001000,
- [5] = 0x002000,
- [6] = 0x000000,
- [7] = 0x004000,
- },
- .inttype_mask = {
- [INTTYPE_EDGE] = 0x3f8000,
- [INTTYPE_NMI] = 0x4000,
- [INTTYPE_SOFTWARE] = 0x880,
- },
- .interrupt = {
- [0] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [1] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [2] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [3] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [4] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [5] = {
- .level = 1,
- .inttype = INTTYPE_LEVEL,
- },
- [6] = {
- .level = 1,
- .inttype = INTTYPE_TIMER,
- },
- [7] = {
- .level = 1,
- .inttype = INTTYPE_SOFTWARE,
- },
- [8] = {
- .level = 2,
- .inttype = INTTYPE_LEVEL,
- },
- [9] = {
- .level = 3,
- .inttype = INTTYPE_LEVEL,
- },
- [10] = {
- .level = 3,
- .inttype = INTTYPE_TIMER,
- },
- [11] = {
- .level = 3,
- .inttype = INTTYPE_SOFTWARE,
- },
- [12] = {
- .level = 4,
- .inttype = INTTYPE_LEVEL,
- },
- [13] = {
- .level = 5,
- .inttype = INTTYPE_TIMER,
- },
- [14] = {
- .level = 7,
- .inttype = INTTYPE_NMI,
- },
- [15] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [16] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [17] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [18] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [19] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [20] = {
- .level = 1,
- .inttype = INTTYPE_EDGE,
- },
- [21] = {
- .level = 3,
- .inttype = INTTYPE_EDGE,
- },
- },
- .nccompare = 3,
- .timerint = {
- [0] = 6,
- [1] = 10,
- [2] = 13,
- },
- .clock_freq_khz = 912000,
- .itlb = {
- .nways = 7,
- .way_size = {
- 4, 4, 4, 4, 4, 2, 2,
- },
- .varway56 = false,
- .nrefillentries = 16,
- },
- .dtlb = {
- .nways = 10,
- .way_size = {
- 4, 4, 4, 4, 4, 2, 2, 1, 1, 1,
- },
- .varway56 = false,
- .nrefillentries = 16,
- },
- },
-};
-
-CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
+ cpu_resume_from_signal(env, NULL);
+ }
+ }
+}
+
+XtensaCPU *cpu_xtensa_init(const char *cpu_model)
{
static int tcg_inited;
+ static int debug_handler_inited;
+ XtensaCPU *cpu;
CPUXtensaState *env;
const XtensaConfig *config = NULL;
- int i;
+ XtensaConfigList *core = xtensa_cores;
- for (i = 0; i < ARRAY_SIZE(core_config); ++i)
- if (strcmp(core_config[i].name, cpu_model) == 0) {
- config = core_config + i;
+ for (; core; core = core->next)
+ if (strcmp(core->config->name, cpu_model) == 0) {
+ config = core->config;
break;
}
return NULL;
}
- env = g_malloc0(sizeof(*env));
+ cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU));
+ env = &cpu->env;
env->config = config;
- cpu_exec_init(env);
if (!tcg_inited) {
tcg_inited = 1;
xtensa_translate_init();
}
+ if (!debug_handler_inited && tcg_enabled()) {
+ debug_handler_inited = 1;
+ cpu_set_debug_excp_handler(breakpoint_handler);
+ }
+
xtensa_irq_init(env);
qemu_init_vcpu(env);
- return env;
+ return cpu;
}
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
- int i;
+ XtensaConfigList *core = xtensa_cores;
cpu_fprintf(f, "Available CPUs:\n");
- for (i = 0; i < ARRAY_SIZE(core_config); ++i) {
- cpu_fprintf(f, " %s\n", core_config[i].name);
+ for (; core; core = core->next) {
+ cpu_fprintf(f, " %s\n", core->config->name);
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
{
uint32_t paddr;
uint32_t page_size;
unsigned access;
- if (xtensa_get_physical_addr(env, addr, 0, 0,
+ if (xtensa_get_physical_addr(env, false, addr, 0, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
- if (xtensa_get_physical_addr(env, addr, 2, 0,
+ if (xtensa_get_physical_addr(env, false, addr, 2, 0,
&paddr, &page_size, &access) == 0) {
return paddr;
}
return ~0;
}
-static uint32_t relocated_vector(CPUState *env, uint32_t vector)
+static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
{
if (xtensa_option_enabled(env->config,
XTENSA_OPTION_RELOCATABLE_VECTOR)) {
* For the level-1 interrupt convert it to either user, kernel or double
* exception with the 'level-1 interrupt' exception cause.
*/
-static void handle_interrupt(CPUState *env)
+static void handle_interrupt(CPUXtensaState *env)
{
int level = env->pending_irq_level;
}
}
-void do_interrupt(CPUState *env)
+void do_interrupt(CPUXtensaState *env)
{
if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
case EXC_KERNEL:
case EXC_USER:
case EXC_DOUBLE:
+ case EXC_DEBUG:
qemu_log_mask(CPU_LOG_INT, "%s(%d) "
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
__func__, env->exception_index,
check_interrupts(env);
}
-static void reset_tlb_mmu_all_ways(CPUState *env,
+static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned wi, ei;
}
}
-static void reset_tlb_mmu_ways56(CPUState *env,
+static void reset_tlb_mmu_ways56(CPUXtensaState *env,
const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
if (!tlb->varway56) {
entry[6][ei].vaddr = ei << 29;
entry[6][ei].paddr = ei << 29;
entry[6][ei].asid = 1;
- entry[6][ei].attr = 2;
+ entry[6][ei].attr = 3;
}
}
}
-static void reset_tlb_region_way0(CPUState *env,
+static void reset_tlb_region_way0(CPUXtensaState *env,
xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
{
unsigned ei;
}
}
-static void reset_mmu(CPUState *env)
+void reset_mmu(CPUXtensaState *env)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
env->sregs[RASID] = 0x04030201;
}
}
-static unsigned get_ring(const CPUState *env, uint8_t asid)
+static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
{
unsigned i;
for (i = 0; i < 4; ++i) {
* \param pring: [out] access ring
* \return 0 if ok, exception cause code otherwise
*/
-int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,
+int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring)
{
const xtensa_tlb *tlb = dtlb ?
static unsigned mmu_attr_to_access(uint32_t attr)
{
unsigned access = 0;
+
if (attr < 12) {
access |= PAGE_READ;
if (attr & 0x1) {
if (attr & 0x2) {
access |= PAGE_WRITE;
}
+
+ switch (attr & 0xc) {
+ case 0:
+ access |= PAGE_CACHE_BYPASS;
+ break;
+
+ case 4:
+ access |= PAGE_CACHE_WB;
+ break;
+
+ case 8:
+ access |= PAGE_CACHE_WT;
+ break;
+ }
} else if (attr == 13) {
- access |= PAGE_READ | PAGE_WRITE;
+ access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
}
return access;
}
*/
static unsigned region_attr_to_access(uint32_t attr)
{
- unsigned access = 0;
- if ((attr < 6 && attr != 3) || attr == 14) {
- access |= PAGE_READ | PAGE_WRITE;
- }
- if (attr > 0 && attr < 6) {
- access |= PAGE_EXEC;
- }
- return access;
+ static const unsigned access[16] = {
+ [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
+ [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
+ [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
+ [3] = PAGE_EXEC | PAGE_CACHE_WB,
+ [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
+ };
+
+ return access[attr & 0xf];
+}
+
+/*!
+ * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
+ * See ISA, A.2.14 The Cache Attribute Register
+ */
+static unsigned cacheattr_attr_to_access(uint32_t attr)
+{
+ static const unsigned access[16] = {
+ [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
+ [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
+ [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
+ [3] = PAGE_EXEC | PAGE_CACHE_WB,
+ [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
+ [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
+ };
+
+ return access[attr & 0xf];
}
static bool is_access_granted(unsigned access, int is_write)
}
}
-static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
- uint32_t *wi, uint32_t *ei, uint8_t *ring);
+static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
-static int get_physical_addr_mmu(CPUState *env,
+static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
- uint32_t *paddr, uint32_t *page_size, unsigned *access)
+ uint32_t *paddr, uint32_t *page_size, unsigned *access,
+ bool may_lookup_pt)
{
bool dtlb = is_write != 2;
uint32_t wi;
uint32_t ei;
uint8_t ring;
+ uint32_t vpn;
+ uint32_t pte;
+ const xtensa_tlb_entry *entry = NULL;
+ xtensa_tlb_entry tmp_entry;
int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
- (mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) &&
- autorefill_mmu(env, vaddr, dtlb, &wi, &ei, &ring) == 0) {
+ may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
+ ring = (pte >> 4) & 0x3;
+ wi = 0;
+ split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
+
+ if (update_tlb) {
+ wi = ++env->autorefill_idx & 0x3;
+ xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
+ env->sregs[EXCVADDR] = vaddr;
+ qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
+ __func__, vaddr, vpn, pte);
+ } else {
+ xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
+ entry = &tmp_entry;
+ }
ret = 0;
}
if (ret != 0) {
return ret;
}
- const xtensa_tlb_entry *entry =
- xtensa_tlb_get_entry(env, dtlb, wi, ei);
+ if (entry == NULL) {
+ entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
+ }
if (ring < mmu_idx) {
return dtlb ?
INST_FETCH_PRIVILEGE_CAUSE;
}
- *access = mmu_attr_to_access(entry->attr);
+ *access = mmu_attr_to_access(entry->attr) &
+ ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
if (!is_access_granted(*access, is_write)) {
return dtlb ?
(is_write ?
return 0;
}
-static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
- uint32_t *wi, uint32_t *ei, uint8_t *ring)
+static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
uint32_t paddr;
uint32_t page_size;
unsigned access;
uint32_t pt_vaddr =
(env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
- int ret = get_physical_addr_mmu(env, pt_vaddr, 0, 0,
- &paddr, &page_size, &access);
+ int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
+ &paddr, &page_size, &access, false);
qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
vaddr, ret ? ~0 : paddr);
if (ret == 0) {
- uint32_t vpn;
- uint32_t pte = ldl_phys(paddr);
-
- *ring = (pte >> 4) & 0x3;
- *wi = (++env->autorefill_idx) & 0x3;
- split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei);
- xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte);
- qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
- __func__, vaddr, vpn, pte);
+ *pte = ldl_phys(paddr);
}
return ret;
}
-static int get_physical_addr_region(CPUState *env,
+static int get_physical_addr_region(CPUXtensaState *env,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
*
* \return 0 if ok, exception cause code otherwise
*/
-int xtensa_get_physical_addr(CPUState *env,
+int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
uint32_t vaddr, int is_write, int mmu_idx,
uint32_t *paddr, uint32_t *page_size, unsigned *access)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
- return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx,
- paddr, page_size, access);
+ return get_physical_addr_mmu(env, update_tlb,
+ vaddr, is_write, mmu_idx, paddr, page_size, access, true);
} else if (xtensa_option_bits_enabled(env->config,
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
} else {
*paddr = vaddr;
*page_size = TARGET_PAGE_SIZE;
- *access = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ *access = cacheattr_attr_to_access(
+ env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
return 0;
}
}
+
+static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
+ CPUXtensaState *env, bool dtlb)
+{
+ unsigned wi, ei;
+ const xtensa_tlb *conf =
+ dtlb ? &env->config->dtlb : &env->config->itlb;
+ unsigned (*attr_to_access)(uint32_t) =
+ xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
+ mmu_attr_to_access : region_attr_to_access;
+
+ for (wi = 0; wi < conf->nways; ++wi) {
+ uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
+ const char *sz_text;
+ bool print_header = true;
+
+ if (sz >= 0x100000) {
+ sz >>= 20;
+ sz_text = "MB";
+ } else {
+ sz >>= 10;
+ sz_text = "KB";
+ }
+
+ for (ei = 0; ei < conf->way_size[wi]; ++ei) {
+ const xtensa_tlb_entry *entry =
+ xtensa_tlb_get_entry(env, dtlb, wi, ei);
+
+ if (entry->asid) {
+ static const char * const cache_text[8] = {
+ [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
+ [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
+ [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
+ [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
+ };
+ unsigned access = attr_to_access(entry->attr);
+ unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
+ PAGE_CACHE_SHIFT;
+
+ if (print_header) {
+ print_header = false;
+ cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
+ cpu_fprintf(f,
+ "\tVaddr Paddr ASID Attr RWX Cache\n"
+ "\t---------- ---------- ---- ---- --- -------\n");
+ }
+ cpu_fprintf(f,
+ "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
+ entry->vaddr,
+ entry->paddr,
+ entry->asid,
+ entry->attr,
+ (access & PAGE_READ) ? 'R' : '-',
+ (access & PAGE_WRITE) ? 'W' : '-',
+ (access & PAGE_EXEC) ? 'X' : '-',
+ cache_text[cache_idx] ? cache_text[cache_idx] :
+ "Invalid");
+ }
+ }
+ }
+}
+
+void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
+{
+ if (xtensa_option_bits_enabled(env->config,
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
+ XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
+
+ cpu_fprintf(f, "ITLB:\n");
+ dump_tlb(f, cpu_fprintf, env, false);
+ cpu_fprintf(f, "\nDTLB:\n");
+ dump_tlb(f, cpu_fprintf, env, true);
+ } else {
+ cpu_fprintf(f, "No TLB for this CPU core\n");
+ }
+}
projects / qemu.git / blobdiff