#include <stdio.h>
#include "cpu.h"
-#include "exec-all.h"
-#include "disas.h"
+#include "exec/exec-all.h"
+#include "disas/disas.h"
#include "tcg-op.h"
-#include "qemu-log.h"
-#include "sysemu.h"
+#include "qemu/log.h"
+#include "sysemu/sysemu.h"
#include "helper.h"
#define GEN_HELPER 1
static TCGv_i32 cpu_SR[256];
static TCGv_i32 cpu_UR[256];
-#include "gen-icount.h"
+#include "exec/gen-icount.h"
typedef struct XtensaReg {
const char *name;
uregnames[i].name);
}
}
-#define GEN_HELPER 2
-#include "helper.h"
}
static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
tcg_temp_free(tmp);
}
-static void gen_advance_ccount(DisasContext *dc)
+static void gen_advance_ccount_cond(DisasContext *dc)
{
if (dc->ccount_delta > 0) {
TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
- dc->ccount_delta = 0;
gen_helper_advance_ccount(cpu_env, tmp);
tcg_temp_free(tmp);
}
}
+static void gen_advance_ccount(DisasContext *dc)
+{
+ gen_advance_ccount_cond(dc);
+ dc->ccount_delta = 0;
+}
+
static void reset_used_window(DisasContext *dc)
{
dc->used_window = 0;
} else {
if (slot >= 0) {
tcg_gen_goto_tb(slot);
- tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
+ tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
} else {
tcg_gen_exit_tb(0);
}
tcg_temp_free(tmp);
}
-static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
+static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
{
if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
if (sregnames[sr].name) {
qemu_log("SR %d is not implemented\n", sr);
}
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
+ return false;
} else if (!(sregnames[sr].access & access)) {
static const char * const access_text[] = {
[SR_R] = "rsr",
qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
access_text[access]);
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
+ return false;
}
+ return true;
}
static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
}
if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
r1 / 4 > dc->used_window) {
- TCGv_i32 pc = tcg_const_i32(dc->pc);
- TCGv_i32 w = tcg_const_i32(r1 / 4);
+ int label = gen_new_label();
+ TCGv_i32 ws = tcg_temp_new_i32();
dc->used_window = r1 / 4;
- gen_advance_ccount(dc);
- gen_helper_window_check(cpu_env, pc, w);
+ tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
+ dc->config->nareg / 4, dc->config->nareg / 4);
+ tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
+ tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
+ {
+ TCGv_i32 pc = tcg_const_i32(dc->pc);
+ TCGv_i32 w = tcg_const_i32(r1 / 4);
+
+ gen_advance_ccount_cond(dc);
+ gen_helper_window_check(cpu_env, pc, w);
- tcg_temp_free(w);
- tcg_temp_free(pc);
+ tcg_temp_free(w);
+ tcg_temp_free(pc);
+ }
+ gen_set_label(label);
+ tcg_temp_free(ws);
}
}
break;
case 6: /*XSR*/
- {
+ if (gen_check_sr(dc, RSR_SR, SR_X)) {
TCGv_i32 tmp = tcg_temp_new_i32();
- gen_check_sr(dc, RSR_SR, SR_X);
+
if (RSR_SR >= 64) {
gen_check_privilege(dc);
}
case 11: /*MULSHi*/
HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
{
- TCGv_i64 r = tcg_temp_new_i64();
- TCGv_i64 s = tcg_temp_new_i64();
- TCGv_i64 t = tcg_temp_new_i64();
+ TCGv lo = tcg_temp_new();
if (OP2 == 10) {
- tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
- tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
+ tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
+ cpu_R[RRR_S], cpu_R[RRR_T]);
} else {
- tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
- tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
+ tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
+ cpu_R[RRR_S], cpu_R[RRR_T]);
}
- tcg_gen_mul_i64(r, s, t);
- tcg_gen_shri_i64(r, r, 32);
- tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
-
- tcg_temp_free_i64(r);
- tcg_temp_free_i64(s);
- tcg_temp_free_i64(t);
+ tcg_temp_free(lo);
}
break;
case 3: /*RST3*/
switch (OP2) {
case 0: /*RSR*/
- gen_check_sr(dc, RSR_SR, SR_R);
- if (RSR_SR >= 64) {
- gen_check_privilege(dc);
+ if (gen_check_sr(dc, RSR_SR, SR_R)) {
+ if (RSR_SR >= 64) {
+ gen_check_privilege(dc);
+ }
+ gen_window_check1(dc, RRR_T);
+ gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
}
- gen_window_check1(dc, RRR_T);
- gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
break;
case 1: /*WSR*/
- gen_check_sr(dc, RSR_SR, SR_W);
- if (RSR_SR >= 64) {
- gen_check_privilege(dc);
+ if (gen_check_sr(dc, RSR_SR, SR_W)) {
+ if (RSR_SR >= 64) {
+ gen_check_privilege(dc);
+ }
+ gen_window_check1(dc, RRR_T);
+ gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
}
- gen_window_check1(dc, RRR_T);
- gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
break;
case 2: /*SEXTu*/
tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
}
} else {
- TCGv_i32 res = tcg_temp_new_i32();
- TCGv_i64 res64 = tcg_temp_new_i64();
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- tcg_gen_mul_i32(res, m1, m2);
- tcg_gen_ext_i32_i64(res64, res);
- tcg_gen_concat_i32_i64(tmp,
- cpu_SR[ACCLO], cpu_SR[ACCHI]);
+ TCGv_i32 lo = tcg_temp_new_i32();
+ TCGv_i32 hi = tcg_temp_new_i32();
+
+ tcg_gen_mul_i32(lo, m1, m2);
+ tcg_gen_sari_i32(hi, lo, 31);
if (op == MAC16_MULA) {
- tcg_gen_add_i64(tmp, tmp, res64);
+ tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+ cpu_SR[ACCLO], cpu_SR[ACCHI],
+ lo, hi);
} else {
- tcg_gen_sub_i64(tmp, tmp, res64);
+ tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+ cpu_SR[ACCLO], cpu_SR[ACCHI],
+ lo, hi);
}
- tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
- tcg_gen_shri_i64(tmp, tmp, 32);
- tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
- tcg_temp_free(res);
- tcg_temp_free_i64(res64);
- tcg_temp_free_i64(tmp);
+ tcg_temp_free_i32(lo);
+ tcg_temp_free_i32(hi);
}
tcg_temp_free(m1);
tcg_temp_free(m2);
}
}
-static void gen_intermediate_code_internal(
- CPUXtensaState *env, TranslationBlock *tb, int search_pc)
+static inline
+void gen_intermediate_code_internal(XtensaCPU *cpu,
+ TranslationBlock *tb, bool search_pc)
{
+ CPUState *cs = CPU(cpu);
+ CPUXtensaState *env = &cpu->env;
DisasContext dc;
int insn_count = 0;
int j, lj = -1;
}
dc.config = env->config;
- dc.singlestep_enabled = env->singlestep_enabled;
+ dc.singlestep_enabled = cs->singlestep_enabled;
dc.tb = tb;
dc.pc = pc_start;
dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
dc.next_icount = tcg_temp_local_new_i32();
}
- gen_icount_start();
+ gen_tb_start();
- if (env->singlestep_enabled && env->exception_taken) {
- env->exception_taken = 0;
+ if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
}
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
}
- if (env->singlestep_enabled) {
+ if (cs->singlestep_enabled) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
gen_exception(&dc, EXCP_DEBUG);
break;
if (dc.is_jmp == DISAS_NEXT) {
gen_jumpi(&dc, dc.pc, 0);
}
- gen_icount_end(tb, insn_count);
+ gen_tb_end(tb, insn_count);
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
- if (!search_pc) {
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("----------------\n");
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ log_target_disas(env, pc_start, dc.pc - pc_start, 0);
+ qemu_log("\n");
+ }
+#endif
+ if (search_pc) {
+ j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
+ memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
+ (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
+ } else {
tb->size = dc.pc - pc_start;
tb->icount = insn_count;
}
void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 0);
+ gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
}
void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
{
- gen_intermediate_code_internal(env, tb, 1);
+ gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
}
-void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf,
- int flags)
+void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
int i, j;
cpu_fprintf(f, "PC=%08x\n\n", env->pc);
projects / qemu.git / blobdiff