spice: add qxl device

[qemu.git] / tcg / README

diff --git a/tcg/README b/tcg/README
index 3d6c170efe301da7aaa9e6071ae17c34b588fa09..68d27ffa6d716641ef77733f948c4fbea7b5458a 100644 (file)
--- a/tcg/README
+++ b/tcg/README
@@ -75,10 +75,13 @@ destroyed, but local temporaries and globals are preserved.
 * Helpers:
 
 Using the tcg_gen_helper_x_y it is possible to call any function
-taking i32, i64 or pointer types. Before calling an helper, all
-globals are stored at their canonical location and it is assumed that
-the function can modify them. In the future, function modifiers will
-be allowed to tell that the helper does not read or write some globals.
+taking i32, i64 or pointer types. By default, before calling an helper,
+all globals are stored at their canonical location and it is assumed
+that the function can modify them. This can be overriden by the
+TCG_CALL_CONST function modifier. By default, the helper is allowed to
+modify the CPU state or raise an exception. This can be overriden by
+the TCG_CALL_PURE function modifier, in which case the call to the
+function is removed if the return value is not used.
 
 On some TCG targets (e.g. x86), several calling conventions are
 supported.
@@ -210,7 +213,7 @@ t0=t1&~t2
 
 * eqv_i32/i64 t0, t1, t2
 
-t0=~(t1^t2)
+t0=~(t1^t2), or equivalently, t0=t1^~t2
 
 * nand_i32/i64 t0, t1, t2
 
@@ -265,13 +268,13 @@ ext32u_i64 t0, t1
 
 * bswap16_i32/i64 t0, t1
 
-16 bit byte swap on a 32/64 bit value. The two/six high order bytes must be
-set to zero.
+16 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
+bytes are set to zero.
 
 * bswap32_i32/i64 t0, t1
 
-32 bit byte swap on a 32/64 bit value. With a 64 bit value, the four high
-order bytes must be set to zero.
+32 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
+the four high order bytes are set to zero.
 
 * bswap64_i64 t0, t1
 
@@ -282,6 +285,14 @@ order bytes must be set to zero.
 Indicate that the value of t0 won't be used later. It is useful to
 force dead code elimination.
 
+********* Conditional moves
+
+* setcond_i32/i64 cond, dest, t1, t2
+
+dest = (t1 cond t2)
+
+Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
+
 ********* Type conversions
 
 * ext_i32_i64 t0, t1
@@ -346,6 +357,11 @@ is returned in two 32-bit outputs.
 Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
 the full 64-bit product T0.  The later is returned in two 32-bit outputs.
 
+* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
+
+Similar to setcond, except that the 64-bit values T1 and T2 are
+formed from two 32-bit arguments.  The result is a 32-bit value.
+
 ********* QEMU specific operations
 
 * tb_exit t0
@@ -362,13 +378,17 @@ instructions.
 qemu_ld8s t0, t1, flags
 qemu_ld16u t0, t1, flags
 qemu_ld16s t0, t1, flags
+qemu_ld32 t0, t1, flags
 qemu_ld32u t0, t1, flags
 qemu_ld32s t0, t1, flags
 qemu_ld64 t0, t1, flags
 
-Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU
-address type. 'flags' contains the QEMU memory index (selects user or
-kernel access) for example.
+Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU address
+type. 'flags' contains the QEMU memory index (selects user or kernel access)
+for example.
+
+Note that "qemu_ld32" implies a 32-bit result, while "qemu_ld32u" and
+"qemu_ld32s" imply a 64-bit result appropriately extended from 32 bits.
 
 * qemu_st8 t0, t1, flags
 qemu_st16 t0, t1, flags