* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#define _GNU_SOURCE
#include <stdlib.h>
#include <sys/mman.h>
#if !defined(__x86_64__)
-#define TEST_VM86
+//#define TEST_VM86
#define TEST_SEGS
#endif
//#define LINUX_VM86_IOPL_FIX
//#define TEST_P4_FLAGS
-#if defined(__x86_64__)
+#ifdef __SSE__
#define TEST_SSE
#define TEST_CMOV 1
#define TEST_FCOMI 1
#else
-//#define TEST_SSE
-#define TEST_CMOV 0
-#define TEST_FCOMI 0
+#undef TEST_SSE
+#define TEST_CMOV 1
+#define TEST_FCOMI 1
#endif
#if defined(__x86_64__)
TEST_JCC("ns", 0, 0);
}
+#define TEST_LOOP(insn) \
+{\
+ for(i = 0; i < sizeof(ecx_vals) / sizeof(long); i++) {\
+ ecx = ecx_vals[i];\
+ for(zf = 0; zf < 2; zf++) {\
+ asm("test %2, %2\n\t"\
+ "movl $1, %0\n\t"\
+ insn " 1f\n\t" \
+ "movl $0, %0\n\t"\
+ "1:\n\t"\
+ : "=a" (res)\
+ : "c" (ecx), "b" (!zf)); \
+ printf("%-10s ECX=" FMTLX " ZF=%ld r=%d\n", insn, ecx, zf, res); \
+ }\
+ }\
+}
+
+void test_loop(void)
+{
+ long ecx, zf;
+ const long ecx_vals[] = {
+ 0,
+ 1,
+ 0x10000,
+ 0x10001,
+#if defined(__x86_64__)
+ 0x100000000L,
+ 0x100000001L,
+#endif
+ };
+ int i, res;
+
+#if !defined(__x86_64__)
+ TEST_LOOP("jcxz");
+ TEST_LOOP("loopw");
+ TEST_LOOP("loopzw");
+ TEST_LOOP("loopnzw");
+#endif
+
+ TEST_LOOP("jecxz");
+ TEST_LOOP("loopl");
+ TEST_LOOP("loopzl");
+ TEST_LOOP("loopnzl");
+}
+
#undef CC_MASK
#ifdef TEST_P4_FLAGS
#define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)
asm("xor %1, %1\n"\
"mov $0x12345678, %0\n"\
#op " %" size "2, %" size "0 ; setz %b1" \
- : "=r" (res), "=q" (resz)\
- : "g" (val));\
+ : "=&r" (res), "=&q" (resz)\
+ : "r" (val));\
printf("%-10s A=" FMTLX " R=" FMTLX " %ld\n", #op, val, res, resz);\
}
op1 = i2l(0xfbca7654);\
asm(#op " %" size "0, %" size "1" \
: "=q" (op0), opconst (op1) \
- : "0" (op0), "1" (op1));\
+ : "0" (op0));\
printf("%-10s A=" FMTLX " B=" FMTLX "\n",\
#op, op0, op1);\
}
op2 = i2l(eax);\
asm(#op " %" size "0, %" size "1" \
: "=q" (op0), opconst (op1) \
- : "0" (op0), "1" (op1), "a" (op2));\
+ : "0" (op0), "a" (op2));\
printf("%-10s EAX=" FMTLX " A=" FMTLX " C=" FMTLX "\n",\
#op, op2, op0, op1);\
}
void test_xchg(void)
{
#if defined(__x86_64__)
- TEST_XCHG(xchgq, "", "=q");
+ TEST_XCHG(xchgq, "", "+q");
#endif
- TEST_XCHG(xchgl, "k", "=q");
- TEST_XCHG(xchgw, "w", "=q");
- TEST_XCHG(xchgb, "b", "=q");
+ TEST_XCHG(xchgl, "k", "+q");
+ TEST_XCHG(xchgw, "w", "+q");
+ TEST_XCHG(xchgb, "b", "+q");
#if defined(__x86_64__)
TEST_XCHG(xchgq, "", "=m");
#endif
- TEST_XCHG(xchgl, "k", "=m");
- TEST_XCHG(xchgw, "w", "=m");
- TEST_XCHG(xchgb, "b", "=m");
+ TEST_XCHG(xchgl, "k", "+m");
+ TEST_XCHG(xchgw, "w", "+m");
+ TEST_XCHG(xchgb, "b", "+m");
#if defined(__x86_64__)
- TEST_XCHG(xaddq, "", "=q");
+ TEST_XCHG(xaddq, "", "+q");
#endif
- TEST_XCHG(xaddl, "k", "=q");
- TEST_XCHG(xaddw, "w", "=q");
- TEST_XCHG(xaddb, "b", "=q");
+ TEST_XCHG(xaddl, "k", "+q");
+ TEST_XCHG(xaddw, "w", "+q");
+ TEST_XCHG(xaddb, "b", "+q");
{
int res;
}
#if defined(__x86_64__)
- TEST_XCHG(xaddq, "", "=m");
+ TEST_XCHG(xaddq, "", "+m");
#endif
- TEST_XCHG(xaddl, "k", "=m");
- TEST_XCHG(xaddw, "w", "=m");
- TEST_XCHG(xaddb, "b", "=m");
+ TEST_XCHG(xaddl, "k", "+m");
+ TEST_XCHG(xaddw, "w", "+m");
+ TEST_XCHG(xaddb, "b", "+m");
#if defined(__x86_64__)
- TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfbca7654);
#endif
- TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfbca7654);
- TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfbca7654);
- TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfbca7654);
#if defined(__x86_64__)
- TEST_CMPXCHG(cmpxchgq, "", "=q", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgq, "", "+q", 0xfffefdfc);
#endif
- TEST_CMPXCHG(cmpxchgl, "k", "=q", 0xfffefdfc);
- TEST_CMPXCHG(cmpxchgw, "w", "=q", 0xfffefdfc);
- TEST_CMPXCHG(cmpxchgb, "b", "=q", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgl, "k", "+q", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgw, "w", "+q", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgb, "b", "+q", 0xfffefdfc);
#if defined(__x86_64__)
- TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfbca7654);
#endif
- TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfbca7654);
- TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfbca7654);
- TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfbca7654);
+ TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfbca7654);
#if defined(__x86_64__)
- TEST_CMPXCHG(cmpxchgq, "", "=m", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgq, "", "+m", 0xfffefdfc);
#endif
- TEST_CMPXCHG(cmpxchgl, "k", "=m", 0xfffefdfc);
- TEST_CMPXCHG(cmpxchgw, "w", "=m", 0xfffefdfc);
- TEST_CMPXCHG(cmpxchgb, "b", "=m", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgl, "k", "+m", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgw, "w", "+m", 0xfffefdfc);
+ TEST_CMPXCHG(cmpxchgb, "b", "+m", 0xfffefdfc);
{
uint64_t op0, op1, op2;
+ long eax, edx;
long i, eflags;
for(i = 0; i < 2; i++) {
op0 = 0x123456789abcdLL;
+ eax = i2l(op0 & 0xffffffff);
+ edx = i2l(op0 >> 32);
if (i == 0)
op1 = 0xfbca765423456LL;
else
op1 = op0;
op2 = 0x6532432432434LL;
- asm("cmpxchg8b %1\n"
+ asm("cmpxchg8b %2\n"
"pushf\n"
- "pop %2\n"
- : "=A" (op0), "=m" (op1), "=g" (eflags)
- : "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
- printf("cmpxchg8b: op0=" FMT64X " op1=" FMT64X " CC=%02lx\n",
- op0, op1, eflags & CC_Z);
+ "pop %3\n"
+ : "=a" (eax), "=d" (edx), "=m" (op1), "=g" (eflags)
+ : "0" (eax), "1" (edx), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
+ printf("cmpxchg8b: eax=" FMTLX " edx=" FMTLX " op1=" FMT64X " CC=%02lx\n",
+ eax, edx, op1, eflags & CC_Z);
}
}
}
#define TEST_LR(op, size, seg, mask)\
{\
int res, res2;\
+ uint16_t mseg = seg;\
res = 0x12345678;\
asm (op " %" size "2, %" size "0\n" \
"movl $0, %1\n"\
"jnz 1f\n"\
"movl $1, %1\n"\
"1:\n"\
- : "=r" (res), "=r" (res2) : "m" (seg), "0" (res));\
+ : "=r" (res), "=r" (res2) : "m" (mseg), "0" (res));\
printf(op ": Z=%d %08x\n", res2, res & ~(mask));\
}
+#define TEST_ARPL(op, size, op1, op2)\
+{\
+ long a, b, c; \
+ a = (op1); \
+ b = (op2); \
+ asm volatile(op " %" size "3, %" size "0\n"\
+ "movl $0,%1\n"\
+ "jnz 1f\n"\
+ "movl $1,%1\n"\
+ "1:\n"\
+ : "=r" (a), "=r" (c) : "0" (a), "r" (b)); \
+ printf(op size " A=" FMTLX " B=" FMTLX " R=" FMTLX " z=%ld\n",\
+ (long)(op1), (long)(op2), a, c);\
+}
+
/* NOTE: we use Linux modify_ldt syscall */
void test_segs(void)
{
TEST_LR("larl", "", 0xfff8, 0);
TEST_LR("lslw", "w", 0xfff8, 0);
TEST_LR("lsll", "", 0xfff8, 0);
+
+ TEST_ARPL("arpl", "w", 0x12345678 | 3, 0x762123c | 1);
+ TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 3);
+ TEST_ARPL("arpl", "w", 0x12345678 | 1, 0x762123c | 1);
}
/* 16 bit code test */
printf("xlat: EAX=" FMTLX "\n", res);
#if defined(__x86_64__)
+#if 0
{
+ /* XXX: see if Intel Core2 and AMD64 behavior really
+ differ. Here we implemented the Intel way which is not
+ compatible yet with QEMU. */
static struct __attribute__((packed)) {
- uint32_t offset;
+ uint64_t offset;
uint16_t seg;
} desc;
long cs_sel;
: "r" (cs_sel) : "memory", "cc");
printf("func_lret=" FMTLX "\n", res);
- /* NOTE: we assume that &func_lret < 4GB */
desc.offset = (long)&func_lret;
desc.seg = cs_sel;
asm volatile ("xor %%rax, %%rax\n"
- "rex64 lcall %1\n"
+ "rex64 lcall *(%%rcx)\n"
: "=a" (res)
- : "m" (desc)
+ : "c" (&desc)
: "memory", "cc");
printf("func_lret2=" FMTLX "\n", res);
asm volatile ("push %2\n"
"mov $ 1f, %%rax\n"
"push %%rax\n"
- "ljmp %1\n"
+ "rex64 ljmp *(%%rcx)\n"
"1:\n"
: "=a" (res)
- : "m" (desc), "b" (cs_sel)
+ : "c" (&desc), "b" (cs_sel)
: "memory", "cc");
printf("func_lret3=" FMTLX "\n", res);
}
+#endif
#else
asm volatile ("push %%cs ; call %1"
: "=a" (res)
0xc3, /* ret */
};
-asm("smc_code2:\n"
+asm(".section \".data\"\n"
+ "smc_code2:\n"
"movl 4(%esp), %eax\n"
"movl %eax, smc_patch_addr2 + 1\n"
"nop\n"
"nop\n"
"smc_patch_addr2:\n"
"movl $1, %eax\n"
- "ret\n");
+ "ret\n"
+ ".previous\n"
+ );
typedef int FuncType(void);
extern int smc_code2(int);
void test_self_modifying_code(void)
{
int i;
-
printf("self modifying code:\n");
printf("func1 = 0x%x\n", ((FuncType *)code)());
for(i = 2; i <= 4; i++) {
#define RBP "%%ebp"
#endif
+#if !defined(__x86_64__)
+/* causes an infinite loop, disable it for now. */
+#define TEST_ENTER(size, stack_type, level)
+#else
#define TEST_ENTER(size, stack_type, level)\
{\
long esp_save, esp_val, ebp_val, ebp_save, i;\
for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
printf(FMTLX "\n", (long)ptr[0]);\
}
+#endif
static void test_enter(void)
{
#ifdef TEST_SSE
typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
-typedef int __m128 __attribute__ ((__mode__(__V4SF__)));
+typedef float __m128 __attribute__ ((__mode__(__V4SF__)));
typedef union {
double d[2];
}
/* Force %xmm0 usage to avoid the case where both register index are 0
- to test intruction decoding more extensively */
+ to test instruction decoding more extensively */
#define CVT_OP_XMM2MMX(op)\
{\
asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
- : "%xmm0");\
+ : "%xmm0"); \
+ asm volatile("emms\n"); \
printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
#op,\
a.q[1], a.q[0],\
#define CVT_OP_MMX2XMM(op)\
{\
asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
+ asm volatile("emms\n"); \
printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
#op,\
a.q[0],\
#if defined(__x86_64__)
TEST_CONV_RAX_RDX(cqo);
#endif
+
+ {
+ unsigned long a, r;
+ a = i2l(0x12345678);
+ asm volatile("bswapl %k0" : "=r" (r) : "0" (a));
+ printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapl", a, r);
+ }
+#if defined(__x86_64__)
+ {
+ unsigned long a, r;
+ a = i2l(0x12345678);
+ asm volatile("bswapq %0" : "=r" (r) : "0" (a));
+ printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapq", a, r);
+ }
+#endif
}
extern void *__start_initcall;
test_bsx();
test_mul();
test_jcc();
+ test_loop();
test_floats();
#if !defined(__x86_64__)
test_bcd();
#ifdef TEST_VM86
test_vm86();
#endif
- test_exceptions();
#if !defined(__x86_64__)
+ test_exceptions();
test_self_modifying_code();
test_single_step();
#endif
projects / qemu.git / blobdiff