#include <inttypes.h>
#include <signal.h>
#include <assert.h>
+#include <sys/mman.h>
+#include "cpu-i386.h"
+#include "exec.h"
#include "disas.h"
-#define DEBUG_DISAS
-
-#define IN_OP_I386
-#include "cpu-i386.h"
-
-#ifndef offsetof
-#define offsetof(type, field) ((size_t) &((type *)0)->field)
-#endif
+//#define DEBUG_MMU
/* XXX: move that elsewhere */
static uint16_t *gen_opc_ptr;
static uint32_t *gen_opparam_ptr;
-int __op_param1, __op_param2, __op_param3;
-
-#ifdef __i386__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __s390__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __ia64__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __powerpc__
-
-#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
-
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
-{
- unsigned long p;
-
- p = start & ~(MIN_CACHE_LINE_SIZE - 1);
- stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
-
- for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm ("dcbst 0,%0;" : : "r"(p) : "memory");
- }
- asm ("sync");
- for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm ("icbi 0,%0; sync;" : : "r"(p) : "memory");
- }
- asm ("sync");
- asm ("isync");
-}
-#endif
-
-#ifdef __alpha__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
- asm ("imb");
-}
-#endif
-
-#ifdef __sparc__
-
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
-{
- unsigned long p;
-
- p = start & ~(8UL - 1UL);
- stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
-
- for (; p < stop; p += 8)
- __asm__ __volatile__("flush\t%0" : : "r" (p));
-}
-
-#endif
-
-extern FILE *logfile;
-extern int loglevel;
#define PREFIX_REPZ 0x01
#define PREFIX_REPNZ 0x02
#define PREFIX_LOCK 0x04
#define PREFIX_DATA 0x08
#define PREFIX_ADR 0x10
-#define PREFIX_FWAIT 0x20
typedef struct DisasContext {
/* current insn context */
int vm86; /* vm86 mode */
int cpl;
int iopl;
+ int tf; /* TF cpu flag */
+ struct TranslationBlock *tb;
+ int popl_esp_hack; /* for correct popl with esp base handling */
} DisasContext;
/* i386 arith/logic operations */
};
enum {
-#define DEF(s, n) INDEX_op_ ## s,
+#define DEF(s, n, copy_size) INDEX_op_ ## s,
#include "opc-i386.h"
#undef DEF
NB_OPS,
};
-#include "op-i386.h"
+#include "gen-op-i386.h"
/* operand size */
enum {
typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
+typedef void (GenOpFunc3)(long, long, long);
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
[OT_BYTE] = {
};
static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
- gen_op_addl_T0_T1_cc,
- gen_op_orl_T0_T1_cc,
NULL,
+ gen_op_orl_T0_T1,
+ NULL,
+ NULL,
+ gen_op_andl_T0_T1,
+ NULL,
+ gen_op_xorl_T0_T1,
NULL,
- gen_op_andl_T0_T1_cc,
- gen_op_subl_T0_T1_cc,
- gen_op_xorl_T0_T1_cc,
- gen_op_cmpl_T0_T1_cc,
};
static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
if (s->addseg && override < 0)
override = R_DS;
if (override >= 0) {
- gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
index = 3 + ot;
} else {
index = ot;
} else {
if (override < 0)
override = R_DS;
- gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
/* 16 address, always override */
index = 6 + ot;
}
JCC_LE,
};
-static GenOpFunc2 *gen_jcc_slow[8] = {
- gen_op_jo_cc,
- gen_op_jb_cc,
- gen_op_jz_cc,
- gen_op_jbe_cc,
- gen_op_js_cc,
- gen_op_jp_cc,
- gen_op_jl_cc,
- gen_op_jle_cc,
-};
-
-static GenOpFunc2 *gen_jcc_sub[3][8] = {
+static GenOpFunc3 *gen_jcc_sub[3][8] = {
[OT_BYTE] = {
NULL,
gen_op_jb_subb,
gen_op_fdiv_STN_ST0,
};
-static void gen_op(DisasContext *s1, int op, int ot, int d, int s)
+/* if d == OR_TMP0, it means memory operand (address in A0) */
+static void gen_op(DisasContext *s1, int op, int ot, int d)
{
- if (d != OR_TMP0)
+ GenOpFunc *gen_update_cc;
+
+ if (d != OR_TMP0) {
gen_op_mov_TN_reg[ot][0][d]();
- if (s != OR_TMP1)
- gen_op_mov_TN_reg[ot][1][s]();
- if (op == OP_ADCL || op == OP_SBBL) {
+ } else {
+ gen_op_ld_T0_A0[ot]();
+ }
+ switch(op) {
+ case OP_ADCL:
+ case OP_SBBL:
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
s1->cc_op = CC_OP_DYNAMIC;
- } else {
+ /* XXX: incorrect: CC_OP must also be modified AFTER memory access */
+ gen_update_cc = gen_op_update2_cc;
+ break;
+ case OP_ADDL:
+ gen_op_addl_T0_T1();
+ s1->cc_op = CC_OP_ADDB + ot;
+ gen_update_cc = gen_op_update2_cc;
+ break;
+ case OP_SUBL:
+ gen_op_subl_T0_T1();
+ s1->cc_op = CC_OP_SUBB + ot;
+ gen_update_cc = gen_op_update2_cc;
+ break;
+ default:
+ case OP_ANDL:
+ case OP_ORL:
+ case OP_XORL:
gen_op_arith_T0_T1_cc[op]();
- s1->cc_op = cc_op_arithb[op] + ot;
+ s1->cc_op = CC_OP_LOGICB + ot;
+ gen_update_cc = gen_op_update1_cc;
+ break;
+ case OP_CMPL:
+ gen_op_cmpl_T0_T1_cc();
+ s1->cc_op = CC_OP_SUBB + ot;
+ gen_update_cc = NULL;
+ break;
}
- if (d != OR_TMP0 && op != OP_CMPL)
- gen_op_mov_reg_T0[ot][d]();
-}
-
-static void gen_opi(DisasContext *s1, int op, int ot, int d, int c)
-{
- gen_op_movl_T1_im(c);
- gen_op(s1, op, ot, d, OR_TMP1);
+ if (op != OP_CMPL) {
+ if (d != OR_TMP0)
+ gen_op_mov_reg_T0[ot][d]();
+ else
+ gen_op_st_T0_A0[ot]();
+ }
+ /* the flags update must happen after the memory write (precise
+ exception support) */
+ if (gen_update_cc)
+ gen_update_cc();
}
+/* if d == OR_TMP0, it means memory operand (address in A0) */
static void gen_inc(DisasContext *s1, int ot, int d, int c)
{
if (d != OR_TMP0)
gen_op_mov_TN_reg[ot][0][d]();
+ else
+ gen_op_ld_T0_A0[ot]();
if (s1->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s1->cc_op);
if (c > 0) {
- gen_op_incl_T0_cc();
+ gen_op_incl_T0();
s1->cc_op = CC_OP_INCB + ot;
} else {
- gen_op_decl_T0_cc();
+ gen_op_decl_T0();
s1->cc_op = CC_OP_DECB + ot;
}
if (d != OR_TMP0)
gen_op_mov_reg_T0[ot][d]();
+ else
+ gen_op_st_T0_A0[ot]();
+ gen_op_update_inc_cc();
}
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
}
if (base >= 0) {
+ /* for correct popl handling with esp */
+ if (base == 4 && s->popl_esp_hack)
+ disp += 4;
gen_op_movl_A0_reg[base]();
if (disp != 0)
gen_op_addl_A0_im(disp);
} else {
gen_op_movl_A0_im(disp);
}
+ /* XXX: index == 4 is always invalid */
if (havesib && (index != 4 || scale != 0)) {
gen_op_addl_A0_reg_sN[scale][index]();
}
else
override = R_DS;
}
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
} else {
switch (mod) {
else
override = R_DS;
}
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
{
+ TranslationBlock *tb;
int inv, jcc_op;
- GenOpFunc2 *func;
+ GenOpFunc3 *func;
inv = b & 1;
jcc_op = (b >> 1) & 7;
case CC_OP_SUBW:
case CC_OP_SUBL:
func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
- if (!func)
- goto slow_jcc;
break;
/* some jumps are easy to compute */
func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
break;
default:
- goto slow_jcc;
+ func = NULL;
+ break;
}
break;
default:
- slow_jcc:
- if (s->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(s->cc_op);
- func = gen_jcc_slow[jcc_op];
+ func = NULL;
break;
}
+
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+
+ if (!func) {
+ gen_setcc_slow[jcc_op]();
+ func = gen_op_jcc;
+ }
+
+ tb = s->tb;
if (!inv) {
- func(val, next_eip);
+ func((long)tb, val, next_eip);
} else {
- func(next_eip, val);
+ func((long)tb, next_eip, val);
}
+ s->is_jmp = 3;
}
static void gen_setcc(DisasContext *s, int b)
}
/* move T0 to seg_reg and compute if the CPU state may change */
-static void gen_movl_seg_T0(DisasContext *s, int seg_reg)
+static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
{
- gen_op_movl_seg_T0(seg_reg);
+ if (!s->vm86)
+ gen_op_movl_seg_T0(seg_reg, cur_eip);
+ else
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
if (!s->addseg && seg_reg < R_FS)
s->is_jmp = 2; /* abort translation because the register may
have a non zero base */
}
}
-static void gen_pop_update(DisasContext *s)
+static inline void gen_stack_update(DisasContext *s, int addend)
{
if (s->ss32) {
- if (s->dflag)
- gen_op_addl_ESP_4();
- else
+ if (addend == 2)
gen_op_addl_ESP_2();
+ else if (addend == 4)
+ gen_op_addl_ESP_4();
+ else
+ gen_op_addl_ESP_im(addend);
} else {
- if (s->dflag)
+ if (addend == 2)
+ gen_op_addw_ESP_2();
+ else if (addend == 4)
gen_op_addw_ESP_4();
else
- gen_op_addw_ESP_2();
+ gen_op_addw_ESP_im(addend);
}
}
+static void gen_pop_update(DisasContext *s)
+{
+ gen_stack_update(s, 2 << s->dflag);
+}
+
+static void gen_stack_A0(DisasContext *s)
+{
+ gen_op_movl_A0_ESP();
+ if (!s->ss32)
+ gen_op_andl_A0_ffff();
+ gen_op_movl_T1_A0();
+ if (s->addseg)
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
+}
+
/* NOTE: wrap around in 16 bit not fully handled */
static void gen_pusha(DisasContext *s)
{
gen_op_andl_A0_ffff();
gen_op_movl_T1_A0();
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
gen_op_st_T0_A0[OT_WORD + s->dflag]();
gen_op_movl_T1_A0();
gen_op_addl_T1_im(16 << s->dflag);
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
gen_op_andl_A0_ffff();
gen_op_movl_T1_A0();
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
/* push bp */
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
gen_op_st_T0_A0[ot]();
gen_op_mov_reg_T1[ot][R_ESP]();
}
+static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
+{
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(cur_eip);
+ gen_op_raise_exception(trapno);
+ s->is_jmp = 1;
+}
+
+/* an interrupt is different from an exception because of the
+ priviledge checks */
+static void gen_interrupt(DisasContext *s, int intno,
+ unsigned int cur_eip, unsigned int next_eip)
+{
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(cur_eip);
+ gen_op_raise_interrupt(intno, next_eip);
+ s->is_jmp = 1;
+}
+
+/* generate a jump to eip. No segment change must happen before as a
+ direct call to the next block may occur */
+static void gen_jmp(DisasContext *s, unsigned int eip)
+{
+ TranslationBlock *tb = s->tb;
+
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_tb_next((long)tb, eip);
+ s->is_jmp = 3;
+}
+
/* return the next pc address. Return -1 if no insn found. *is_jmp_ptr
is set to true if the instruction sets the PC (last instruction of
a basic block) */
case 0x67:
prefixes |= PREFIX_ADR;
goto next_byte;
- case 0x9b:
- prefixes |= PREFIX_FWAIT;
- goto next_byte;
}
if (prefixes & PREFIX_DATA)
rm = modrm & 7;
if (mod != 3) {
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0[ot]();
opreg = OR_TMP0;
} else {
opreg = OR_EAX + rm;
}
- gen_op(s, op, ot, opreg, reg);
- if (mod != 3 && op != 7) {
- gen_op_st_T0_A0[ot]();
- }
+ gen_op_mov_TN_reg[ot][1][reg]();
+ gen_op(s, op, ot, opreg);
break;
case 1: /* OP Gv, Ev */
modrm = ldub(s->pc++);
if (mod != 3) {
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
gen_op_ld_T1_A0[ot]();
- opreg = OR_TMP1;
} else {
- opreg = OR_EAX + rm;
+ gen_op_mov_TN_reg[ot][1][rm]();
}
- gen_op(s, op, ot, reg, opreg);
+ gen_op(s, op, ot, reg);
break;
case 2: /* OP A, Iv */
val = insn_get(s, ot);
- gen_opi(s, op, ot, OR_EAX, val);
+ gen_op_movl_T1_im(val);
+ gen_op(s, op, ot, OR_EAX);
break;
}
}
if (mod != 3) {
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
- gen_op_ld_T0_A0[ot]();
opreg = OR_TMP0;
} else {
opreg = rm + OR_EAX;
val = (int8_t)insn_get(s, OT_BYTE);
break;
}
-
- gen_opi(s, op, ot, opreg, val);
- if (op != 7 && mod != 3) {
- gen_op_st_T0_A0[ot]();
- }
+ gen_op_movl_T1_im(val);
+ gen_op(s, op, ot, opreg);
}
break;
}
break;
case 3: /* neg */
- gen_op_negl_T0_cc();
+ gen_op_negl_T0();
if (mod != 3) {
gen_op_st_T0_A0[ot]();
} else {
gen_op_mov_reg_T0[ot][rm]();
}
+ gen_op_update_neg_cc();
s->cc_op = CC_OP_SUBB + ot;
break;
case 4: /* mul */
case 6: /* div */
switch(ot) {
case OT_BYTE:
- gen_op_divb_AL_T0();
+ gen_op_divb_AL_T0(pc_start - s->cs_base);
break;
case OT_WORD:
- gen_op_divw_AX_T0();
+ gen_op_divw_AX_T0(pc_start - s->cs_base);
break;
default:
case OT_LONG:
- gen_op_divl_EAX_T0();
+ gen_op_divl_EAX_T0(pc_start - s->cs_base);
break;
}
break;
case 7: /* idiv */
switch(ot) {
case OT_BYTE:
- gen_op_idivb_AL_T0();
+ gen_op_idivb_AL_T0(pc_start - s->cs_base);
break;
case OT_WORD:
- gen_op_idivw_AX_T0();
+ gen_op_idivw_AX_T0(pc_start - s->cs_base);
break;
default:
case OT_LONG:
- gen_op_idivl_EAX_T0();
+ gen_op_idivl_EAX_T0(pc_start - s->cs_base);
break;
}
break;
}
if (mod != 3) {
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
- if (op != 3 && op != 5)
+ if (op >= 2 && op != 3 && op != 5)
gen_op_ld_T0_A0[ot]();
} else {
gen_op_mov_TN_reg[ot][0][rm]();
switch(op) {
case 0: /* inc Ev */
- gen_inc(s, ot, OR_TMP0, 1);
if (mod != 3)
- gen_op_st_T0_A0[ot]();
+ opreg = OR_TMP0;
else
- gen_op_mov_reg_T0[ot][rm]();
+ opreg = rm;
+ gen_inc(s, ot, opreg, 1);
break;
case 1: /* dec Ev */
- gen_inc(s, ot, OR_TMP0, -1);
if (mod != 3)
- gen_op_st_T0_A0[ot]();
+ opreg = OR_TMP0;
else
- gen_op_mov_reg_T0[ot][rm]();
+ opreg = rm;
+ gen_inc(s, ot, opreg, -1);
break;
case 2: /* call Ev */
/* XXX: optimize if memory (no and is necessary) */
gen_op_ld_T1_A0[ot]();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_movl_T0_T1();
gen_op_jmp_T0();
s->is_jmp = 1;
gen_op_ld_T1_A0[ot]();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, R_CS);
- gen_op_movl_T0_T1();
- gen_op_jmp_T0();
+ if (!s->vm86) {
+ /* we compute EIP to handle the exception case */
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_ljmp_T0_T1();
+ } else {
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
+ gen_op_movl_T0_T1();
+ gen_op_jmp_T0();
+ }
s->is_jmp = 1;
break;
case 6: /* push Ev */
rm = modrm & 7;
gen_op_mov_TN_reg[ot][0][reg]();
gen_op_mov_TN_reg[ot][1][rm]();
- gen_op_addl_T0_T1_cc();
+ gen_op_addl_T0_T1();
gen_op_mov_reg_T0[ot][rm]();
gen_op_mov_reg_T1[ot][reg]();
} else {
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
gen_op_mov_TN_reg[ot][0][reg]();
gen_op_ld_T1_A0[ot]();
- gen_op_addl_T0_T1_cc();
+ gen_op_addl_T0_T1();
gen_op_st_T0_A0[ot]();
gen_op_mov_reg_T1[ot][reg]();
}
+ gen_op_update2_cc();
s->cc_op = CC_OP_ADDB + ot;
break;
case 0x1b0:
ot = dflag ? OT_LONG : OT_WORD;
modrm = ldub(s->pc++);
gen_pop_T0(s);
+ s->popl_esp_hack = 1;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+ s->popl_esp_hack = 0;
gen_pop_update(s);
break;
case 0xc8: /* enter */
}
break;
case 0xc9: /* leave */
- /* XXX: exception not precise (ESP is update before potential exception) */
+ /* XXX: exception not precise (ESP is updated before potential exception) */
if (s->ss32) {
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
gen_op_mov_reg_T0[OT_LONG][R_ESP]();
case 0x17: /* pop ss */
case 0x1f: /* pop ds */
gen_pop_T0(s);
- gen_movl_seg_T0(s, b >> 3);
+ gen_movl_seg_T0(s, b >> 3, pc_start - s->cs_base);
gen_pop_update(s);
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
gen_pop_T0(s);
- gen_movl_seg_T0(s, (b >> 3) & 7);
+ gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
gen_pop_update(s);
break;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
if (reg >= 6 || reg == R_CS)
goto illegal_op;
- gen_movl_seg_T0(s, reg);
+ gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
break;
case 0x8c: /* mov Gv, seg */
ot = dflag ? OT_LONG : OT_WORD;
override = R_DS;
}
if (must_add_seg) {
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
if ((b & 2) == 0) {
override = R_DS;
}
if (must_add_seg) {
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
gen_op_ldub_T0_A0();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
/* load the segment first to handle exceptions properly */
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, op);
+ gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1[ot][reg]();
break;
break;
}
break;
+ case 0x0c: /* fldenv mem */
+ gen_op_fldenv_A0(s->dflag);
+ break;
case 0x0d: /* fldcw mem */
gen_op_fldcw_A0();
break;
+ case 0x0e: /* fnstenv mem */
+ gen_op_fnstenv_A0(s->dflag);
+ break;
case 0x0f: /* fnstcw mem */
gen_op_fnstcw_A0();
break;
gen_op_fstt_ST0_A0();
gen_op_fpop();
break;
+ case 0x2c: /* frstor mem */
+ gen_op_frstor_A0(s->dflag);
+ break;
+ case 0x2e: /* fnsave mem */
+ gen_op_fnsave_A0(s->dflag);
+ break;
case 0x2f: /* fnstsw mem */
gen_op_fnstsw_A0();
break;
break;
case 0x1c:
switch(rm) {
+ case 0: /* feni (287 only, just do nop here) */
+ break;
+ case 1: /* fdisi (287 only, just do nop here) */
+ break;
case 2: /* fclex */
gen_op_fclex();
break;
case 3: /* fninit */
gen_op_fninit();
break;
+ case 4: /* fsetpm (287 only, just do nop here) */
+ break;
default:
goto illegal_op;
}
break;
+ case 0x1d: /* fucomi */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fucomi_ST0_FT0();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
+ case 0x1e: /* fcomi */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fcomi_ST0_FT0();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
case 0x2a: /* fst sti */
gen_op_fmov_STN_ST0(opreg);
break;
goto illegal_op;
}
break;
+ case 0x3d: /* fucomip */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fucomi_ST0_FT0();
+ gen_op_fpop();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
+ case 0x3e: /* fcomip */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fcomi_ST0_FT0();
+ gen_op_fpop();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
default:
goto illegal_op;
}
case 0x6d:
if (s->cpl > s->iopl || s->vm86) {
/* NOTE: even for (E)CX = 0 the exception is raised */
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
case 0x6f:
if (s->cpl > s->iopl || s->vm86) {
/* NOTE: even for (E)CX = 0 the exception is raised */
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
case 0xe4:
case 0xe5:
if (s->cpl > s->iopl || s->vm86) {
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
case 0xe6:
case 0xe7:
if (s->cpl > s->iopl || s->vm86) {
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
case 0xec:
case 0xed:
if (s->cpl > s->iopl || s->vm86) {
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
case 0xee:
case 0xef:
if (s->cpl > s->iopl || s->vm86) {
- gen_op_gpf(pc_start - s->cs_base);
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
if ((b & 1) == 0)
ot = OT_BYTE;
val = ldsw(s->pc);
s->pc += 2;
gen_pop_T0(s);
- if (s->ss32)
- gen_op_addl_ESP_im(val + (2 << s->dflag));
- else
- gen_op_addw_ESP_im(val + (2 << s->dflag));
+ gen_stack_update(s, val + (2 << s->dflag));
if (s->dflag == 0)
gen_op_andl_T0_ffff();
gen_op_jmp_T0();
s->is_jmp = 1;
break;
case 0xca: /* lret im */
- /* XXX: not restartable */
val = ldsw(s->pc);
s->pc += 2;
+ do_lret:
+ gen_stack_A0(s);
/* pop offset */
- gen_pop_T0(s);
+ gen_op_ld_T0_A0[1 + s->dflag]();
if (s->dflag == 0)
gen_op_andl_T0_ffff();
+ /* NOTE: keeping EIP updated is not a problem in case of
+ exception */
gen_op_jmp_T0();
- gen_pop_update(s);
/* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
+ gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_ld_T0_A0[1 + s->dflag]();
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
/* add stack offset */
- if (s->ss32)
- gen_op_addl_ESP_im(val + (2 << s->dflag));
- else
- gen_op_addw_ESP_im(val + (2 << s->dflag));
+ gen_stack_update(s, val + (4 << s->dflag));
s->is_jmp = 1;
break;
case 0xcb: /* lret */
- /* XXX: not restartable */
- /* pop offset */
- gen_pop_T0(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
- gen_op_jmp_T0();
- gen_pop_update(s);
- /* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
- s->is_jmp = 1;
- break;
+ val = 0;
+ goto do_lret;
case 0xcf: /* iret */
- /* XXX: not restartable */
- /* pop offset */
- gen_pop_T0(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
- gen_op_jmp_T0();
- gen_pop_update(s);
- /* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
- /* pop eflags */
- gen_pop_T0(s);
- if (s->dflag) {
- if (s->vm86)
- gen_op_movl_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movl_eflags_T0();
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- if (s->vm86)
- gen_op_movw_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movw_eflags_T0();
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_iret_protected(s->dflag);
+ s->cc_op = CC_OP_EFLAGS;
}
- gen_pop_update(s);
- s->cc_op = CC_OP_EFLAGS;
s->is_jmp = 1;
break;
case 0xe8: /* call im */
val &= 0xffff;
gen_op_movl_T0_im(next_eip);
gen_push_T0(s);
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
}
break;
case 0x9a: /* lcall im */
{
unsigned int selector, offset;
+ /* XXX: not restartable */
ot = dflag ? OT_LONG : OT_WORD;
offset = insn_get(s, ot);
/* change cs and pc */
gen_op_movl_T0_im(selector);
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_jmp_im((unsigned long)offset);
s->is_jmp = 1;
}
val += s->pc - s->cs_base;
if (s->dflag == 0)
val = val & 0xffff;
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
break;
case 0xea: /* ljmp im */
{
/* change cs and pc */
gen_op_movl_T0_im(selector);
- gen_movl_seg_T0(s, R_CS);
- gen_op_jmp_im((unsigned long)offset);
+ if (!s->vm86) {
+ /* we compute EIP to handle the exception case */
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_movl_T1_im(offset);
+ gen_op_ljmp_T0_T1();
+ } else {
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
+ gen_op_jmp_im((unsigned long)offset);
+ }
s->is_jmp = 1;
}
break;
val += s->pc - s->cs_base;
if (s->dflag == 0)
val = val & 0xffff;
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
break;
case 0x70 ... 0x7f: /* jcc Jb */
val = (int8_t)insn_get(s, OT_BYTE);
if (s->dflag == 0)
val &= 0xffff;
gen_jcc(s, b, val, next_eip);
- s->is_jmp = 1;
break;
case 0x190 ... 0x19f: /* setcc Gv */
/************************/
/* flags */
case 0x9c: /* pushf */
- if (s->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(s->cc_op);
- if (s->vm86)
- gen_op_movl_T0_eflags_vm();
- else
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
gen_op_movl_T0_eflags();
- gen_push_T0(s);
+ gen_push_T0(s);
+ }
break;
case 0x9d: /* popf */
- gen_pop_T0(s);
- if (s->dflag) {
- if (s->vm86)
- gen_op_movl_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movl_eflags_T0();
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- if (s->vm86)
- gen_op_movw_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movw_eflags_T0();
+ gen_pop_T0(s);
+ if (s->cpl == 0) {
+ if (s->dflag) {
+ gen_op_movl_eflags_T0_cpl0();
+ } else {
+ gen_op_movw_eflags_T0_cpl0();
+ }
+ } else {
+ if (s->dflag) {
+ gen_op_movl_eflags_T0();
+ } else {
+ gen_op_movw_eflags_T0();
+ }
+ }
+ gen_pop_update(s);
+ s->cc_op = CC_OP_EFLAGS;
+ s->is_jmp = 2; /* abort translation because TF flag may change */
}
- gen_pop_update(s);
- s->cc_op = CC_OP_EFLAGS;
break;
case 0x9e: /* sahf */
gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
/* misc */
case 0x90: /* nop */
break;
+ case 0x9b: /* fwait */
+ break;
case 0xcc: /* int3 */
- gen_op_int3((long)pc_start);
- s->is_jmp = 1;
+ gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
break;
case 0xcd: /* int N */
val = ldub(s->pc++);
- gen_op_int_im(val, pc_start - s->cs_base);
- s->is_jmp = 1;
+ /* XXX: add error code for vm86 GPF */
+ if (!s->vm86)
+ gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
+ else
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
case 0xce: /* into */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
- gen_op_into();
+ gen_op_into(s->pc - s->cs_base);
break;
case 0xfa: /* cli */
if (!s->vm86) {
- if (s->cpl <= s->iopl)
+ if (s->cpl <= s->iopl) {
gen_op_cli();
- else
- gen_op_gpf(pc_start - s->cs_base);
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
} else {
- if (s->iopl == 3)
+ if (s->iopl == 3) {
gen_op_cli();
- else
- gen_op_cli_vm();
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
}
break;
case 0xfb: /* sti */
if (!s->vm86) {
- if (s->cpl <= s->iopl)
+ if (s->cpl <= s->iopl) {
gen_op_sti();
- else
- gen_op_gpf(pc_start - s->cs_base);
+ s->is_jmp = 2; /* give a chance to handle pending irqs */
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
} else {
- if (s->iopl == 3)
+ if (s->iopl == 3) {
gen_op_sti();
- else
- gen_op_sti_vm(pc_start - s->cs_base);
+ s->is_jmp = 2; /* give a chance to handle pending irqs */
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
}
break;
case 0x62: /* bound */
gen_op_mov_reg_T0[ot][reg]();
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
if (ot == OT_WORD)
- gen_op_boundw();
+ gen_op_boundw(pc_start - s->cs_base);
else
- gen_op_boundl();
+ gen_op_boundl(pc_start - s->cs_base);
break;
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = b & 7;
gen_op_cpuid();
break;
case 0xf4: /* hlt */
- if (s->cpl == 0) {
- /* ignored */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_op_gpf(pc_start - s->cs_base);
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(s->pc - s->cs_base);
+ gen_op_hlt();
+ s->is_jmp = 1;
+ }
+ break;
+ case 0x100:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* sldt */
+ gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
+ ot = OT_WORD;
+ if (mod == 3)
+ ot += s->dflag;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+ break;
+ case 2: /* lldt */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_lldt_T0();
+ }
+ break;
+ case 1: /* str */
+ gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
+ ot = OT_WORD;
+ if (mod == 3)
+ ot += s->dflag;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+ break;
+ case 3: /* ltr */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_ltr_T0();
+ }
+ break;
+ case 4: /* verr */
+ case 5: /* verw */
+ default:
+ goto illegal_op;
+ }
+ break;
+ case 0x101:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* sgdt */
+ case 1: /* sidt */
+ if (mod == 3)
+ goto illegal_op;
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ if (op == 0)
+ gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
+ else
+ gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
+ gen_op_stw_T0_A0();
+ gen_op_addl_A0_im(2);
+ if (op == 0)
+ gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
+ else
+ gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
+ if (!s->dflag)
+ gen_op_andl_T0_im(0xffffff);
+ gen_op_stl_T0_A0();
+ break;
+ case 2: /* lgdt */
+ case 3: /* lidt */
+ if (mod == 3)
+ goto illegal_op;
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ gen_op_lduw_T1_A0();
+ gen_op_addl_A0_im(2);
+ gen_op_ldl_T0_A0();
+ if (!s->dflag)
+ gen_op_andl_T0_im(0xffffff);
+ if (op == 2) {
+ gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
+ gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
+ } else {
+ gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
+ gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
+ }
+ }
+ break;
+ case 4: /* smsw */
+ gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
+ break;
+ case 6: /* lmsw */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_lmsw_T0();
+ }
+ break;
+ case 7: /* invlpg */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if (mod == 3)
+ goto illegal_op;
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ gen_op_invlpg_A0();
+ }
+ break;
+ default:
+ goto illegal_op;
+ }
+ break;
+ case 0x102: /* lar */
+ case 0x103: /* lsl */
+ if (s->vm86)
+ goto illegal_op;
+ ot = dflag ? OT_LONG : OT_WORD;
+ modrm = ldub(s->pc++);
+ reg = (modrm >> 3) & 7;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+ gen_op_mov_TN_reg[ot][1][reg]();
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ if (b == 0x102)
+ gen_op_lar();
+ else
+ gen_op_lsl();
+ s->cc_op = CC_OP_EFLAGS;
+ gen_op_mov_reg_T1[ot][reg]();
+ break;
+ case 0x118:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* prefetchnta */
+ case 1: /* prefetchnt0 */
+ case 2: /* prefetchnt0 */
+ case 3: /* prefetchnt0 */
+ if (mod == 3)
+ goto illegal_op;
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ /* nothing more to do */
+ break;
+ default:
+ goto illegal_op;
+ }
+ break;
+ case 0x120: /* mov reg, crN */
+ case 0x122: /* mov crN, reg */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ modrm = ldub(s->pc++);
+ if ((modrm & 0xc0) != 0xc0)
+ goto illegal_op;
+ rm = modrm & 7;
+ reg = (modrm >> 3) & 7;
+ switch(reg) {
+ case 0:
+ case 2:
+ case 3:
+ case 4:
+ if (b & 2) {
+ gen_op_mov_TN_reg[OT_LONG][0][rm]();
+ gen_op_movl_crN_T0(reg);
+ s->is_jmp = 2;
+ } else {
+ gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
+ gen_op_mov_reg_T0[OT_LONG][rm]();
+ }
+ break;
+ default:
+ goto illegal_op;
+ }
+ }
+ break;
+ case 0x121: /* mov reg, drN */
+ case 0x123: /* mov drN, reg */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ modrm = ldub(s->pc++);
+ if ((modrm & 0xc0) != 0xc0)
+ goto illegal_op;
+ rm = modrm & 7;
+ reg = (modrm >> 3) & 7;
+ /* XXX: do it dynamically with CR4.DE bit */
+ if (reg == 4 || reg == 5)
+ goto illegal_op;
+ if (b & 2) {
+ gen_op_mov_TN_reg[OT_LONG][0][rm]();
+ gen_op_movl_drN_T0(reg);
+ s->is_jmp = 2;
+ } else {
+ gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
+ gen_op_mov_reg_T0[OT_LONG][rm]();
+ }
+ }
+ break;
+ case 0x106: /* clts */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_op_clts();
}
break;
default:
[INDEX_op_sbbl_T0_T1_cc] = CC_C,
/* subtle: due to the incl/decl implementation, C is used */
- [INDEX_op_incl_T0_cc] = CC_C,
- [INDEX_op_decl_T0_cc] = CC_C,
+ [INDEX_op_update_inc_cc] = CC_C,
[INDEX_op_into] = CC_O,
- [INDEX_op_jo_cc] = CC_O,
- [INDEX_op_jb_cc] = CC_C,
- [INDEX_op_jz_cc] = CC_Z,
- [INDEX_op_jbe_cc] = CC_Z | CC_C,
- [INDEX_op_js_cc] = CC_S,
- [INDEX_op_jp_cc] = CC_P,
- [INDEX_op_jl_cc] = CC_O | CC_S,
- [INDEX_op_jle_cc] = CC_O | CC_S | CC_Z,
-
[INDEX_op_jb_subb] = CC_C,
[INDEX_op_jb_subw] = CC_C,
[INDEX_op_jb_subl] = CC_C,
[INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
- [INDEX_op_movl_T0_eflags_vm] = CC_OSZAPC,
[INDEX_op_cmc] = CC_C,
[INDEX_op_salc] = CC_C,
/* flags written by an operation */
static uint16_t opc_write_flags[NB_OPS] = {
- [INDEX_op_addl_T0_T1_cc] = CC_OSZAPC,
- [INDEX_op_orl_T0_T1_cc] = CC_OSZAPC,
+ [INDEX_op_update2_cc] = CC_OSZAPC,
+ [INDEX_op_update1_cc] = CC_OSZAPC,
[INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
- [INDEX_op_andl_T0_T1_cc] = CC_OSZAPC,
- [INDEX_op_subl_T0_T1_cc] = CC_OSZAPC,
- [INDEX_op_xorl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
- [INDEX_op_negl_T0_cc] = CC_OSZAPC,
+ [INDEX_op_update_neg_cc] = CC_OSZAPC,
/* subtle: due to the incl/decl implementation, C is used */
- [INDEX_op_incl_T0_cc] = CC_OSZAPC,
- [INDEX_op_decl_T0_cc] = CC_OSZAPC,
+ [INDEX_op_update_inc_cc] = CC_OSZAPC,
[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
[INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
- [INDEX_op_movw_eflags_T0_vm] = CC_OSZAPC,
[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
- [INDEX_op_movl_eflags_T0_vm] = CC_OSZAPC,
[INDEX_op_clc] = CC_C,
[INDEX_op_stc] = CC_C,
[INDEX_op_cmc] = CC_C,
[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
[INDEX_op_cmpxchg8b] = CC_Z,
+ [INDEX_op_lar] = CC_Z,
+ [INDEX_op_lsl] = CC_Z,
+ [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
+ [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
};
/* simpler form of an operation if no flags need to be generated */
static uint16_t opc_simpler[NB_OPS] = {
- [INDEX_op_addl_T0_T1_cc] = INDEX_op_addl_T0_T1,
- [INDEX_op_orl_T0_T1_cc] = INDEX_op_orl_T0_T1,
- [INDEX_op_andl_T0_T1_cc] = INDEX_op_andl_T0_T1,
- [INDEX_op_subl_T0_T1_cc] = INDEX_op_subl_T0_T1,
- [INDEX_op_xorl_T0_T1_cc] = INDEX_op_xorl_T0_T1,
- [INDEX_op_negl_T0_cc] = INDEX_op_negl_T0,
- [INDEX_op_incl_T0_cc] = INDEX_op_incl_T0,
- [INDEX_op_decl_T0_cc] = INDEX_op_decl_T0,
+ [INDEX_op_update2_cc] = INDEX_op_nop,
+ [INDEX_op_update1_cc] = INDEX_op_nop,
+ [INDEX_op_update_neg_cc] = INDEX_op_nop,
+ [INDEX_op_update_inc_cc] = INDEX_op_nop,
[INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
[INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
}
}
-
-#ifdef DEBUG_DISAS
-static const char *op_str[] = {
-#define DEF(s, n) #s,
-#include "opc-i386.h"
-#undef DEF
-};
-
-static uint8_t op_nb_args[] = {
-#define DEF(s, n) n,
-#include "opc-i386.h"
-#undef DEF
-};
-
-static void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
-{
- const uint16_t *opc_ptr;
- const uint32_t *opparam_ptr;
- int c, n, i;
-
- opc_ptr = opc_buf;
- opparam_ptr = opparam_buf;
- for(;;) {
- c = *opc_ptr++;
- n = op_nb_args[c];
- fprintf(logfile, "0x%04x: %s", opc_ptr - opc_buf - 1, op_str[c]);
- for(i = 0; i < n; i++) {
- fprintf(logfile, " 0x%x", opparam_ptr[i]);
- }
- fprintf(logfile, "\n");
- if (c == INDEX_op_end)
- break;
- opparam_ptr += n;
- }
-}
-
-#endif
-
-/* XXX: make this buffer thread safe */
-/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 32
-#define OPC_BUF_SIZE 512
-#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
-
-#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
-
-static uint16_t gen_opc_buf[OPC_BUF_SIZE];
-static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
-
-/* return non zero if the very first instruction is invalid so that
- the virtual CPU can trigger an exception. */
-int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size,
- int *gen_code_size_ptr,
- uint8_t *pc_start, uint8_t *cs_base, int flags)
+/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
+ basic block 'tb'. If search_pc is TRUE, also generate PC
+ information for each intermediate instruction. */
+static inline int gen_intermediate_code_internal(TranslationBlock *tb, int search_pc)
{
DisasContext dc1, *dc = &dc1;
uint8_t *pc_ptr;
uint16_t *gen_opc_end;
- int gen_code_size;
+ int flags, j, lj;
long ret;
+ uint8_t *pc_start;
+ uint8_t *cs_base;
/* generate intermediate code */
-
+ pc_start = (uint8_t *)tb->pc;
+ cs_base = (uint8_t *)tb->cs_base;
+ flags = tb->flags;
+
dc->code32 = (flags >> GEN_FLAG_CODE32_SHIFT) & 1;
dc->ss32 = (flags >> GEN_FLAG_SS32_SHIFT) & 1;
dc->addseg = (flags >> GEN_FLAG_ADDSEG_SHIFT) & 1;
dc->vm86 = (flags >> GEN_FLAG_VM_SHIFT) & 1;
dc->cpl = (flags >> GEN_FLAG_CPL_SHIFT) & 3;
dc->iopl = (flags >> GEN_FLAG_IOPL_SHIFT) & 3;
+ dc->tf = (flags >> GEN_FLAG_TF_SHIFT) & 1;
dc->cc_op = CC_OP_DYNAMIC;
dc->cs_base = cs_base;
-
+ dc->tb = tb;
+ dc->popl_esp_hack = 0;
+
gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
gen_opparam_ptr = gen_opparam_buf;
- dc->is_jmp = 0;
+ dc->is_jmp = DISAS_NEXT;
pc_ptr = pc_start;
+ lj = -1;
do {
+ if (search_pc) {
+ j = gen_opc_ptr - gen_opc_buf;
+ if (lj < j) {
+ lj++;
+ while (lj < j)
+ gen_opc_instr_start[lj++] = 0;
+ gen_opc_pc[lj] = (uint32_t)pc_ptr;
+ gen_opc_cc_op[lj] = dc->cc_op;
+ gen_opc_instr_start[lj] = 1;
+ }
+ }
ret = disas_insn(dc, pc_ptr);
if (ret == -1) {
/* we trigger an illegal instruction operation only if it
break;
}
pc_ptr = (void *)ret;
- } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end);
+ /* if single step mode, we generate only one instruction and
+ generate an exception */
+ if (dc->tf)
+ break;
+ } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
+ (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
/* we must store the eflags state if it is not already done */
- if (dc->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(dc->cc_op);
- if (dc->is_jmp != 1) {
- /* we add an additionnal jmp to update the simulated PC */
- gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
+ if (dc->is_jmp != DISAS_TB_JUMP) {
+ if (dc->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(dc->cc_op);
+ if (dc->is_jmp != DISAS_JUMP) {
+ /* we add an additionnal jmp to update the simulated PC */
+ gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
+ }
+ }
+ if (dc->tf) {
+ gen_op_raise_exception(EXCP01_SSTP);
+ }
+ if (dc->is_jmp != 3) {
+ /* indicate that the hash table must be used to find the next TB */
+ gen_op_movl_T0_0();
}
*gen_opc_ptr = INDEX_op_end;
if (loglevel) {
fprintf(logfile, "----------------\n");
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
- disas(logfile, pc_start, pc_ptr - pc_start,
- dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
+ disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
fprintf(logfile, "\n");
fprintf(logfile, "OP:\n");
fprintf(logfile, "\n");
}
#endif
+ if (!search_pc)
+ tb->size = pc_ptr - pc_start;
+ return 0;
+}
- /* generate machine code */
- gen_code_size = dyngen_code(gen_code_buf, gen_opc_buf, gen_opparam_buf);
- flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
- *gen_code_size_ptr = gen_code_size;
+int gen_intermediate_code(TranslationBlock *tb)
+{
+ return gen_intermediate_code_internal(tb, 0);
+}
-#ifdef DEBUG_DISAS
- if (loglevel) {
- fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
- disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
- fprintf(logfile, "\n");
- fflush(logfile);
- }
-#endif
- return 0;
+int gen_intermediate_code_pc(TranslationBlock *tb)
+{
+ return gen_intermediate_code_internal(tb, 1);
}
CPUX86State *cpu_x86_init(void)
int i;
static int inited;
- cpu_x86_tblocks_init();
+ cpu_exec_init();
env = malloc(sizeof(CPUX86State));
if (!env)
{
free(env);
}
+
+/***********************************************************/
+/* x86 mmu */
+/* XXX: add PGE support */
+
+/* called when cr3 or PG bit are modified */
+static int last_pg_state = -1;
+int phys_ram_size;
+int phys_ram_fd;
+uint8_t *phys_ram_base;
+
+void cpu_x86_update_cr0(CPUX86State *env)
+{
+ int pg_state;
+ void *map_addr;
+
+#ifdef DEBUG_MMU
+ printf("CR0 update: CR0=0x%08x\n", env->cr[0]);
+#endif
+ pg_state = env->cr[0] & CR0_PG_MASK;
+ if (pg_state != last_pg_state) {
+ if (!pg_state) {
+ /* we map the physical memory at address 0 */
+
+ map_addr = mmap((void *)0, phys_ram_size, PROT_WRITE | PROT_READ,
+ MAP_SHARED | MAP_FIXED, phys_ram_fd, 0);
+ if (map_addr == MAP_FAILED) {
+ fprintf(stderr,
+ "Could not map physical memory at host address 0x%08x\n",
+ 0);
+ exit(1);
+ }
+ page_set_flags(0, phys_ram_size,
+ PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC);
+ } else {
+ /* we unmap the physical memory */
+ munmap((void *)0, phys_ram_size);
+ page_set_flags(0, phys_ram_size, 0);
+ }
+ last_pg_state = pg_state;
+ }
+}
+
+void cpu_x86_update_cr3(CPUX86State *env)
+{
+ if (env->cr[0] & CR0_PG_MASK) {
+#ifdef DEBUG_MMU
+ printf("CR3 update: CR3=%08x\n", env->cr[3]);
+#endif
+ page_unmap();
+ }
+}
+
+void cpu_x86_init_mmu(CPUX86State *env)
+{
+ last_pg_state = -1;
+ cpu_x86_update_cr0(env);
+}
+
+/* XXX: also flush 4MB pages */
+void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
+{
+ int flags;
+ unsigned long virt_addr;
+
+ flags = page_get_flags(addr);
+ if (flags & PAGE_VALID) {
+ virt_addr = addr & ~0xfff;
+ munmap((void *)virt_addr, 4096);
+ page_set_flags(virt_addr, virt_addr + 4096, 0);
+ }
+}
+
+/* return value:
+ -1 = cannot handle fault
+ 0 = nothing more to do
+ 1 = generate PF fault
+*/
+int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr, int is_write)
+{
+ uint8_t *pde_ptr, *pte_ptr;
+ uint32_t pde, pte, virt_addr;
+ int cpl, error_code, is_dirty, is_user, prot, page_size;
+ void *map_addr;
+
+ cpl = env->segs[R_CS].selector & 3;
+ is_user = (cpl == 3);
+
+#ifdef DEBUG_MMU
+ printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
+ addr, is_write, is_user, env->eip);
+#endif
+
+ if (env->user_mode_only) {
+ /* user mode only emulation */
+ error_code = 0;
+ goto do_fault;
+ }
+
+ if (!(env->cr[0] & CR0_PG_MASK))
+ return -1;
+
+ /* page directory entry */
+ pde_ptr = phys_ram_base + ((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3));
+ pde = ldl(pde_ptr);
+ if (!(pde & PG_PRESENT_MASK)) {
+ error_code = 0;
+ goto do_fault;
+ }
+ if (is_user) {
+ if (!(pde & PG_USER_MASK))
+ goto do_fault_protect;
+ if (is_write && !(pde & PG_RW_MASK))
+ goto do_fault_protect;
+ } else {
+ if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) &&
+ is_write && !(pde & PG_RW_MASK))
+ goto do_fault_protect;
+ }
+ /* if PSE bit is set, then we use a 4MB page */
+ if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
+ is_dirty = is_write && !(pde & PG_DIRTY_MASK);
+ if (!(pde & PG_ACCESSED_MASK)) {
+ pde |= PG_ACCESSED_MASK;
+ if (is_dirty)
+ pde |= PG_DIRTY_MASK;
+ stl(pde_ptr, pde);
+ }
+
+ pte = pde & ~0x003ff000; /* align to 4MB */
+ page_size = 4096 * 1024;
+ virt_addr = addr & ~0x003fffff;
+ } else {
+ if (!(pde & PG_ACCESSED_MASK)) {
+ pde |= PG_ACCESSED_MASK;
+ stl(pde_ptr, pde);
+ }
+
+ /* page directory entry */
+ pte_ptr = phys_ram_base + ((pde & ~0xfff) + ((addr >> 10) & 0xffc));
+ pte = ldl(pte_ptr);
+ if (!(pte & PG_PRESENT_MASK)) {
+ error_code = 0;
+ goto do_fault;
+ }
+ if (is_user) {
+ if (!(pte & PG_USER_MASK))
+ goto do_fault_protect;
+ if (is_write && !(pte & PG_RW_MASK))
+ goto do_fault_protect;
+ } else {
+ if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) &&
+ is_write && !(pte & PG_RW_MASK))
+ goto do_fault_protect;
+ }
+ is_dirty = is_write && !(pte & PG_DIRTY_MASK);
+ if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
+ pte |= PG_ACCESSED_MASK;
+ if (is_dirty)
+ pte |= PG_DIRTY_MASK;
+ stl(pte_ptr, pte);
+ }
+ page_size = 4096;
+ virt_addr = addr & ~0xfff;
+ }
+ /* the page can be put in the TLB */
+ prot = PROT_READ;
+ if (is_user) {
+ if (pte & PG_RW_MASK)
+ prot |= PROT_WRITE;
+ } else {
+ if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) ||
+ (pte & PG_RW_MASK))
+ prot |= PROT_WRITE;
+ }
+ map_addr = mmap((void *)virt_addr, page_size, prot,
+ MAP_SHARED | MAP_FIXED, phys_ram_fd, pte & ~0xfff);
+ if (map_addr == MAP_FAILED) {
+ fprintf(stderr,
+ "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
+ pte & ~0xfff, virt_addr);
+ exit(1);
+ }
+ page_set_flags(virt_addr, virt_addr + page_size,
+ PAGE_VALID | PAGE_EXEC | prot);
+#ifdef DEBUG_MMU
+ printf("mmaping 0x%08x to virt 0x%08x pse=%d\n",
+ pte & ~0xfff, virt_addr, (page_size != 4096));
+#endif
+ return 0;
+ do_fault_protect:
+ error_code = PG_ERROR_P_MASK;
+ do_fault:
+ env->cr[2] = addr;
+ env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
+ if (is_user)
+ env->error_code |= PG_ERROR_U_MASK;
+ return 1;
+}
+
+/***********************************************************/
+/* x86 debug */
+
+static const char *cc_op_str[] = {
+ "DYNAMIC",
+ "EFLAGS",
+ "MUL",
+ "ADDB",
+ "ADDW",
+ "ADDL",
+ "ADCB",
+ "ADCW",
+ "ADCL",
+ "SUBB",
+ "SUBW",
+ "SUBL",
+ "SBBB",
+ "SBBW",
+ "SBBL",
+ "LOGICB",
+ "LOGICW",
+ "LOGICL",
+ "INCB",
+ "INCW",
+ "INCL",
+ "DECB",
+ "DECW",
+ "DECL",
+ "SHLB",
+ "SHLW",
+ "SHLL",
+ "SARB",
+ "SARW",
+ "SARL",
+};
+
+void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
+{
+ int eflags;
+ char cc_op_name[32];
+
+ eflags = env->eflags;
+ fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
+ "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
+ "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]\n",
+ env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
+ env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
+ env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-');
+ fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
+ env->segs[R_CS].selector,
+ env->segs[R_SS].selector,
+ env->segs[R_DS].selector,
+ env->segs[R_ES].selector,
+ env->segs[R_FS].selector,
+ env->segs[R_GS].selector);
+ if (flags & X86_DUMP_CCOP) {
+ if ((unsigned)env->cc_op < CC_OP_NB)
+ strcpy(cc_op_name, cc_op_str[env->cc_op]);
+ else
+ snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
+ fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
+ env->cc_src, env->cc_dst, cc_op_name);
+ }
+ if (flags & X86_DUMP_FPU) {
+ fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
+ (double)env->fpregs[0],
+ (double)env->fpregs[1],
+ (double)env->fpregs[2],
+ (double)env->fpregs[3]);
+ fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
+ (double)env->fpregs[4],
+ (double)env->fpregs[5],
+ (double)env->fpregs[7],
+ (double)env->fpregs[8]);
+ }
+}
projects / qemu.git / blobdiff