#include "cpu-i386.h"
#include "disas.h"
+#include "thunk.h"
+
+#include "vl.h"
#define DEBUG_LOGFILE "/tmp/vl.log"
#define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
+#define BIOS_FILENAME "bios.bin"
+#define VGABIOS_FILENAME "vgabios.bin"
//#define DEBUG_UNUSED_IOPORT
-#define PHYS_RAM_BASE 0xa8000000
+//#define DEBUG_IRQ_LATENCY
+
+/* output Bochs bios info messages */
+//#define DEBUG_BIOS
+
+/* debug IDE devices */
+//#define DEBUG_IDE
+
+/* debug PIC */
+//#define DEBUG_PIC
+
+/* debug NE2000 card */
+//#define DEBUG_NE2000
+
+/* debug PC keyboard */
+//#define DEBUG_KBD
+
+/* debug PC keyboard : only mouse */
+//#define DEBUG_MOUSE
+
+#define PHYS_RAM_BASE 0xac000000
+#define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
+
#define KERNEL_LOAD_ADDR 0x00100000
#define INITRD_LOAD_ADDR 0x00400000
#define KERNEL_PARAMS_ADDR 0x00090000
+#define GUI_REFRESH_INTERVAL 30
+
+#define MAX_DISKS 2
+
/* from plex86 (BSD license) */
struct __attribute__ ((packed)) linux_params {
// For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
#define KERNEL_CS 0x10
#define KERNEL_DS 0x18
-typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
-typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
-
-#define MAX_IOPORTS 1024
+#define MAX_IOPORTS 4096
+static const char *interp_prefix = CONFIG_QEMU_PREFIX;
char phys_ram_file[1024];
CPUX86State *global_env;
CPUX86State *cpu_single_env;
FILE *logfile = NULL;
int loglevel;
-IOPortReadFunc *ioport_readb_table[MAX_IOPORTS];
-IOPortWriteFunc *ioport_writeb_table[MAX_IOPORTS];
-IOPortReadFunc *ioport_readw_table[MAX_IOPORTS];
-IOPortWriteFunc *ioport_writew_table[MAX_IOPORTS];
+IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
+IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
+BlockDriverState *bs_table[MAX_DISKS];
+int vga_ram_size;
+static DisplayState display_state;
+int nodisp;
+int term_inited;
+int64_t ticks_per_sec;
/***********************************************************/
/* x86 io ports */
#ifdef DEBUG_UNUSED_IOPORT
fprintf(stderr, "inb: port=0x%04x\n", address);
#endif
- return 0;
+ return 0xff;
}
void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
{
uint32_t data;
- data = ioport_readb_table[address](env, address);
- data |= ioport_readb_table[address + 1](env, address + 1) << 8;
+ data = ioport_read_table[0][address & (MAX_IOPORTS - 1)](env, address);
+ data |= ioport_read_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1) << 8;
return data;
}
void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
{
- ioport_writeb_table[address](env, address, data & 0xff);
- ioport_writeb_table[address + 1](env, address + 1, (data >> 8) & 0xff);
+ ioport_write_table[0][address & (MAX_IOPORTS - 1)](env, address, data & 0xff);
+ ioport_write_table[0][(address + 1) & (MAX_IOPORTS - 1)](env, address + 1, (data >> 8) & 0xff);
}
-void init_ioports(void)
+uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
{
- int i;
-
- for(i = 0; i < MAX_IOPORTS; i++) {
- ioport_readb_table[i] = default_ioport_readb;
- ioport_writeb_table[i] = default_ioport_writeb;
- ioport_readw_table[i] = default_ioport_readw;
- ioport_writew_table[i] = default_ioport_writew;
- }
+#ifdef DEBUG_UNUSED_IOPORT
+ fprintf(stderr, "inl: port=0x%04x\n", address);
+#endif
+ return 0xffffffff;
}
-int register_ioport_readb(int start, int length, IOPortReadFunc *func)
+void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
{
- int i;
-
- for(i = start; i < start + length; i++)
- ioport_readb_table[i] = func;
- return 0;
+#ifdef DEBUG_UNUSED_IOPORT
+ fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
+#endif
}
-int register_ioport_writeb(int start, int length, IOPortWriteFunc *func)
+void init_ioports(void)
{
int i;
- for(i = start; i < start + length; i++)
- ioport_writeb_table[i] = func;
- return 0;
+ for(i = 0; i < MAX_IOPORTS; i++) {
+ ioport_read_table[0][i] = default_ioport_readb;
+ ioport_write_table[0][i] = default_ioport_writeb;
+ ioport_read_table[1][i] = default_ioport_readw;
+ ioport_write_table[1][i] = default_ioport_writew;
+ ioport_read_table[2][i] = default_ioport_readl;
+ ioport_write_table[2][i] = default_ioport_writel;
+ }
}
-int register_ioport_readw(int start, int length, IOPortReadFunc *func)
+/* size is the word size in byte */
+int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
{
- int i;
+ int i, bsize;
- for(i = start; i < start + length; i += 2)
- ioport_readw_table[i] = func;
+ if (size == 1)
+ bsize = 0;
+ else if (size == 2)
+ bsize = 1;
+ else if (size == 4)
+ bsize = 2;
+ else
+ return -1;
+ for(i = start; i < start + length; i += size)
+ ioport_read_table[bsize][i] = func;
return 0;
}
-int register_ioport_writew(int start, int length, IOPortWriteFunc *func)
+/* size is the word size in byte */
+int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
{
- int i;
+ int i, bsize;
- for(i = start; i < start + length; i += 2)
- ioport_writew_table[i] = func;
+ if (size == 1)
+ bsize = 0;
+ else if (size == 2)
+ bsize = 1;
+ else if (size == 4)
+ bsize = 2;
+ else
+ return -1;
+ for(i = start; i < start + length; i += size)
+ ioport_write_table[bsize][i] = func;
return 0;
}
void cpu_x86_outb(CPUX86State *env, int addr, int val)
{
- ioport_writeb_table[addr & (MAX_IOPORTS - 1)](env, addr, val);
+ ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
}
void cpu_x86_outw(CPUX86State *env, int addr, int val)
{
- ioport_writew_table[addr & (MAX_IOPORTS - 1)](env, addr, val);
+ ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
}
void cpu_x86_outl(CPUX86State *env, int addr, int val)
{
- fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
+ ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
}
int cpu_x86_inb(CPUX86State *env, int addr)
{
- return ioport_readb_table[addr & (MAX_IOPORTS - 1)](env, addr);
+ return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
}
int cpu_x86_inw(CPUX86State *env, int addr)
{
- return ioport_readw_table[addr & (MAX_IOPORTS - 1)](env, addr);
+ return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
}
int cpu_x86_inl(CPUX86State *env, int addr)
{
- fprintf(stderr, "inl: port=0x%04x\n", addr);
- return 0;
+ return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
}
/***********************************************************/
abort();
}
-/***********************************************************/
-/* vga emulation */
-static uint8_t vga_index;
-static uint8_t vga_regs[256];
-static int last_cursor_pos;
-
-void update_console_messages(void)
-{
- int c, i, cursor_pos, eol;
-
- cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
- eol = 0;
- for(i = last_cursor_pos; i < cursor_pos; i++) {
- c = phys_ram_base[0xb8000 + (i) * 2];
- if (c >= ' ') {
- putchar(c);
- eol = 0;
- } else {
- if (!eol)
- putchar('\n');
- eol = 1;
- }
- }
- fflush(stdout);
- last_cursor_pos = cursor_pos;
-}
-
-/* just to see first Linux console messages, we intercept cursor position */
-void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
-{
- switch(addr) {
- case 0x3d4:
- vga_index = data;
- break;
- case 0x3d5:
- vga_regs[vga_index] = data;
- if (vga_index == 0x0f)
- update_console_messages();
- break;
- }
-
-}
-
/***********************************************************/
/* cmos emulation */
{
struct tm *tm;
time_t ti;
+ int val;
ti = time(NULL);
tm = gmtime(&ti);
cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
- cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon);
+ cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
cmos_data[RTC_REG_A] = 0x26;
cmos_data[RTC_REG_C] = 0x00;
cmos_data[RTC_REG_D] = 0x80;
- cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
+ /* various important CMOS locations needed by PC/Bochs bios */
- register_ioport_writeb(0x70, 2, cmos_ioport_write);
- register_ioport_readb(0x70, 2, cmos_ioport_read);
+ cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
+ cmos_data[REG_EQUIPMENT_BYTE] |= 0x04; /* PS/2 mouse installed */
+
+ /* memory size */
+ val = (phys_ram_size / 1024) - 1024;
+ if (val > 65535)
+ val = 65535;
+ cmos_data[0x17] = val;
+ cmos_data[0x18] = val >> 8;
+ cmos_data[0x30] = val;
+ cmos_data[0x31] = val >> 8;
+
+ val = (phys_ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
+ if (val > 65535)
+ val = 65535;
+ cmos_data[0x34] = val;
+ cmos_data[0x35] = val >> 8;
+
+ cmos_data[0x3d] = 0x02; /* hard drive boot */
+
+ register_ioport_write(0x70, 2, cmos_ioport_write, 1);
+ register_ioport_read(0x70, 2, cmos_ioport_read, 1);
}
/***********************************************************/
}
}
-void pic_set_irq(int irq, int level)
-{
- pic_set_irq1(&pics[irq >> 3], irq & 7, level);
-}
-
-/* can be called at any time outside cpu_exec() to raise irqs if
- necessary */
-void pic_handle_irq(void)
+/* raise irq to CPU if necessary. must be called every time the active
+ irq may change */
+static void pic_update_irq(void)
{
int irq2, irq;
/* from master pic */
pic_irq_requested = irq;
}
- global_env->hard_interrupt_request = 1;
+ cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
+ }
+}
+
+#ifdef DEBUG_IRQ_LATENCY
+int64_t irq_time[16];
+int64_t cpu_get_ticks(void);
+#endif
+#if defined(DEBUG_PIC)
+int irq_level[16];
+#endif
+
+void pic_set_irq(int irq, int level)
+{
+#if defined(DEBUG_PIC)
+ if (level != irq_level[irq]) {
+ printf("pic_set_irq: irq=%d level=%d\n", irq, level);
+ irq_level[irq] = level;
}
+#endif
+#ifdef DEBUG_IRQ_LATENCY
+ if (level) {
+ irq_time[irq] = cpu_get_ticks();
+ }
+#endif
+ pic_set_irq1(&pics[irq >> 3], irq & 7, level);
+ pic_update_irq();
}
int cpu_x86_get_pic_interrupt(CPUX86State *env)
/* signal the pic that the irq was acked by the CPU */
irq = pic_irq_requested;
+#ifdef DEBUG_IRQ_LATENCY
+ printf("IRQ%d latency=%0.3fus\n",
+ irq,
+ (double)(cpu_get_ticks() - irq_time[irq]) * 1000000.0 / ticks_per_sec);
+#endif
+#ifdef DEBUG_PIC
+ printf("pic_interrupt: irq=%d\n", irq);
+#endif
+
if (irq >= 8) {
irq2 = irq & 7;
pics[1].isr |= (1 << irq2);
PicState *s;
int priority;
+#ifdef DEBUG_PIC
+ printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
+#endif
s = &pics[addr >> 7];
addr &= 1;
if (addr == 0) {
}
if (val == 0xa0)
s->priority_add = (s->priority_add + 1) & 7;
+ pic_update_irq();
break;
case 0x60 ... 0x67:
priority = val & 7;
s->isr &= ~(1 << priority);
+ pic_update_irq();
break;
case 0xc0 ... 0xc7:
s->priority_add = (val + 1) & 7;
+ pic_update_irq();
break;
case 0xe0 ... 0xe7:
priority = val & 7;
s->isr &= ~(1 << priority);
s->priority_add = (priority + 1) & 7;
+ pic_update_irq();
break;
}
}
case 0:
/* normal mode */
s->imr = val;
+ pic_update_irq();
break;
case 1:
s->irq_base = val & 0xf8;
}
}
-uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr)
+uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
{
PicState *s;
+ unsigned int addr;
+ int ret;
+
+ addr = addr1;
s = &pics[addr >> 7];
addr &= 1;
if (addr == 0) {
if (s->read_reg_select)
- return s->isr;
+ ret = s->isr;
else
- return s->irr;
+ ret = s->irr;
} else {
- return s->imr;
+ ret = s->imr;
}
+#ifdef DEBUG_PIC
+ printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
+#endif
+ return ret;
}
void pic_init(void)
{
- register_ioport_writeb(0x20, 2, pic_ioport_write);
- register_ioport_readb(0x20, 2, pic_ioport_read);
- register_ioport_writeb(0xa0, 2, pic_ioport_write);
- register_ioport_readb(0xa0, 2, pic_ioport_read);
+ register_ioport_write(0x20, 2, pic_ioport_write, 1);
+ register_ioport_read(0x20, 2, pic_ioport_read, 1);
+ register_ioport_write(0xa0, 2, pic_ioport_write, 1);
+ register_ioport_read(0xa0, 2, pic_ioport_read, 1);
}
/***********************************************************/
PITChannelState pit_channels[3];
int speaker_data_on;
+int dummy_refresh_clock;
int pit_min_timer_count = 0;
-int64_t ticks_per_sec;
-
int64_t get_clock(void)
{
struct timeval tv;
{
int out;
out = pit_get_out(&pit_channels[2]);
- return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5);
+ dummy_refresh_clock ^= 1;
+ return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5) |
+ (dummy_refresh_clock << 4);
}
void pit_init(void)
pit_load_count(s, 0);
}
- register_ioport_writeb(0x40, 4, pit_ioport_write);
- register_ioport_readb(0x40, 3, pit_ioport_read);
+ register_ioport_write(0x40, 4, pit_ioport_write, 1);
+ register_ioport_read(0x40, 3, pit_ioport_read, 1);
- register_ioport_readb(0x61, 1, speaker_ioport_read);
- register_ioport_writeb(0x61, 1, speaker_ioport_write);
+ register_ioport_read(0x61, 1, speaker_ioport_read, 1);
+ register_ioport_write(0x61, 1, speaker_ioport_write, 1);
}
/***********************************************************/
printf("\n"
"C-a h print this help\n"
"C-a x exit emulatior\n"
+ "C-a s save disk data back to file (if -snapshot)\n"
"C-a b send break (magic sysrq)\n"
"C-a C-a send C-a\n"
);
case 'x':
exit(0);
break;
+ case 's':
+ {
+ int i;
+ for (i = 0; i < MAX_DISKS; i++) {
+ if (bs_table[i])
+ bdrv_commit(bs_table[i]);
+ }
+ }
+ break;
case 'b':
/* send break */
s->rbr = 0;
}
}
-/* init terminal so that we can grab keys */
-static struct termios oldtty;
-
-static void term_exit(void)
-{
- tcsetattr (0, TCSANOW, &oldtty);
-}
-
-static void term_init(void)
-{
- struct termios tty;
-
- tcgetattr (0, &tty);
- oldtty = tty;
-
- tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
- |INLCR|IGNCR|ICRNL|IXON);
- tty.c_oflag |= OPOST;
- tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
- tty.c_cflag &= ~(CSIZE|PARENB);
- tty.c_cflag |= CS8;
- tty.c_cc[VMIN] = 1;
- tty.c_cc[VTIME] = 0;
-
- tcsetattr (0, TCSANOW, &tty);
-
- atexit(term_exit);
-
- fcntl(0, F_SETFL, O_NONBLOCK);
-}
-
void serial_init(void)
{
SerialState *s = &serial_ports[0];
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
- register_ioport_writeb(0x3f8, 8, serial_ioport_write);
- register_ioport_readb(0x3f8, 8, serial_ioport_read);
-
- term_init();
+ register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
+ register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
}
/***********************************************************/
/* ne2000 emulation */
-//#define DEBUG_NE2000
-
#define NE2000_IOPORT 0x300
#define NE2000_IRQ 9
close(fd);
return -1;
}
- printf("connected to host network interface: %s\n", ifr.ifr_name);
+ printf("Connected to host network interface: %s\n", ifr.ifr_name);
fcntl(fd, F_SETFL, O_NONBLOCK);
net_fd = fd;
s->rcnt == 0) {
s->isr |= ENISR_RDC;
ne2000_update_irq(s);
- /* XXX: find a better solution for irqs */
- cpu_x86_interrupt(global_env);
}
if (val & E8390_TRANS) {
net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
void ne2000_init(void)
{
- register_ioport_writeb(NE2000_IOPORT, 16, ne2000_ioport_write);
- register_ioport_readb(NE2000_IOPORT, 16, ne2000_ioport_read);
+ register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
+ register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
- register_ioport_writeb(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write);
- register_ioport_readb(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read);
- register_ioport_writew(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write);
- register_ioport_readw(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read);
+ register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
+ register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
+ register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
+ register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
- register_ioport_writeb(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write);
- register_ioport_readb(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read);
+ register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
+ register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
ne2000_reset();
}
/***********************************************************/
-/* cpu signal handler */
-static void host_segv_handler(int host_signum, siginfo_t *info,
- void *puc)
-{
- if (cpu_signal_handler(host_signum, info, puc))
- return;
- term_exit();
- abort();
+/* ide emulation */
+
+/* Bits of HD_STATUS */
+#define ERR_STAT 0x01
+#define INDEX_STAT 0x02
+#define ECC_STAT 0x04 /* Corrected error */
+#define DRQ_STAT 0x08
+#define SEEK_STAT 0x10
+#define SRV_STAT 0x10
+#define WRERR_STAT 0x20
+#define READY_STAT 0x40
+#define BUSY_STAT 0x80
+
+/* Bits for HD_ERROR */
+#define MARK_ERR 0x01 /* Bad address mark */
+#define TRK0_ERR 0x02 /* couldn't find track 0 */
+#define ABRT_ERR 0x04 /* Command aborted */
+#define MCR_ERR 0x08 /* media change request */
+#define ID_ERR 0x10 /* ID field not found */
+#define MC_ERR 0x20 /* media changed */
+#define ECC_ERR 0x40 /* Uncorrectable ECC error */
+#define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
+#define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
+
+/* Bits of HD_NSECTOR */
+#define CD 0x01
+#define IO 0x02
+#define REL 0x04
+#define TAG_MASK 0xf8
+
+#define IDE_CMD_RESET 0x04
+#define IDE_CMD_DISABLE_IRQ 0x02
+
+/* ATA/ATAPI Commands pre T13 Spec */
+#define WIN_NOP 0x00
+/*
+ * 0x01->0x02 Reserved
+ */
+#define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
+/*
+ * 0x04->0x07 Reserved
+ */
+#define WIN_SRST 0x08 /* ATAPI soft reset command */
+#define WIN_DEVICE_RESET 0x08
+/*
+ * 0x09->0x0F Reserved
+ */
+#define WIN_RECAL 0x10
+#define WIN_RESTORE WIN_RECAL
+/*
+ * 0x10->0x1F Reserved
+ */
+#define WIN_READ 0x20 /* 28-Bit */
+#define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
+#define WIN_READ_LONG 0x22 /* 28-Bit */
+#define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
+#define WIN_READ_EXT 0x24 /* 48-Bit */
+#define WIN_READDMA_EXT 0x25 /* 48-Bit */
+#define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
+#define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
+/*
+ * 0x28
+ */
+#define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
+/*
+ * 0x2A->0x2F Reserved
+ */
+#define WIN_WRITE 0x30 /* 28-Bit */
+#define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
+#define WIN_WRITE_LONG 0x32 /* 28-Bit */
+#define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
+#define WIN_WRITE_EXT 0x34 /* 48-Bit */
+#define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
+#define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
+#define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
+#define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
+#define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
+/*
+ * 0x3A->0x3B Reserved
+ */
+#define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
+/*
+ * 0x3D->0x3F Reserved
+ */
+#define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
+#define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
+#define WIN_VERIFY_EXT 0x42 /* 48-Bit */
+/*
+ * 0x43->0x4F Reserved
+ */
+#define WIN_FORMAT 0x50
+/*
+ * 0x51->0x5F Reserved
+ */
+#define WIN_INIT 0x60
+/*
+ * 0x61->0x5F Reserved
+ */
+#define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
+#define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
+#define WIN_DIAGNOSE 0x90
+#define WIN_SPECIFY 0x91 /* set drive geometry translation */
+#define WIN_DOWNLOAD_MICROCODE 0x92
+#define WIN_STANDBYNOW2 0x94
+#define WIN_STANDBY2 0x96
+#define WIN_SETIDLE2 0x97
+#define WIN_CHECKPOWERMODE2 0x98
+#define WIN_SLEEPNOW2 0x99
+/*
+ * 0x9A VENDOR
+ */
+#define WIN_PACKETCMD 0xA0 /* Send a packet command. */
+#define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
+#define WIN_QUEUED_SERVICE 0xA2
+#define WIN_SMART 0xB0 /* self-monitoring and reporting */
+#define CFA_ERASE_SECTORS 0xC0
+#define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
+#define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
+#define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
+#define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
+#define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
+#define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
+#define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
+#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
+#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
+#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
+#define WIN_GETMEDIASTATUS 0xDA
+#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
+#define WIN_POSTBOOT 0xDC
+#define WIN_PREBOOT 0xDD
+#define WIN_DOORLOCK 0xDE /* lock door on removable drives */
+#define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
+#define WIN_STANDBYNOW1 0xE0
+#define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
+#define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
+#define WIN_SETIDLE1 0xE3
+#define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
+#define WIN_CHECKPOWERMODE1 0xE5
+#define WIN_SLEEPNOW1 0xE6
+#define WIN_FLUSH_CACHE 0xE7
+#define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
+#define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
+ /* SET_FEATURES 0x22 or 0xDD */
+#define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
+#define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
+#define WIN_MEDIAEJECT 0xED
+#define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
+#define WIN_SETFEATURES 0xEF /* set special drive features */
+#define EXABYTE_ENABLE_NEST 0xF0
+#define WIN_SECURITY_SET_PASS 0xF1
+#define WIN_SECURITY_UNLOCK 0xF2
+#define WIN_SECURITY_ERASE_PREPARE 0xF3
+#define WIN_SECURITY_ERASE_UNIT 0xF4
+#define WIN_SECURITY_FREEZE_LOCK 0xF5
+#define WIN_SECURITY_DISABLE 0xF6
+#define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
+#define WIN_SET_MAX 0xF9
+#define DISABLE_SEAGATE 0xFB
+
+/* set to 1 set disable mult support */
+#define MAX_MULT_SECTORS 8
+
+struct IDEState;
+
+typedef void EndTransferFunc(struct IDEState *);
+
+typedef struct IDEState {
+ /* ide config */
+ int cylinders, heads, sectors;
+ int64_t nb_sectors;
+ int mult_sectors;
+ int irq;
+ /* ide regs */
+ uint8_t feature;
+ uint8_t error;
+ uint16_t nsector; /* 0 is 256 to ease computations */
+ uint8_t sector;
+ uint8_t lcyl;
+ uint8_t hcyl;
+ uint8_t select;
+ uint8_t status;
+ /* 0x3f6 command, only meaningful for drive 0 */
+ uint8_t cmd;
+ /* depends on bit 4 in select, only meaningful for drive 0 */
+ struct IDEState *cur_drive;
+ BlockDriverState *bs;
+ int req_nb_sectors; /* number of sectors per interrupt */
+ EndTransferFunc *end_transfer_func;
+ uint8_t *data_ptr;
+ uint8_t *data_end;
+ uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
+} IDEState;
+
+IDEState ide_state[MAX_DISKS];
+
+static void padstr(char *str, const char *src, int len)
+{
+ int i, v;
+ for(i = 0; i < len; i++) {
+ if (*src)
+ v = *src++;
+ else
+ v = ' ';
+ *(char *)((long)str ^ 1) = v;
+ str++;
+ }
}
-static int timer_irq_pending;
-static int timer_irq_count;
+static void ide_identify(IDEState *s)
+{
+ uint16_t *p;
+ unsigned int oldsize;
+
+ memset(s->io_buffer, 0, 512);
+ p = (uint16_t *)s->io_buffer;
+ stw(p + 0, 0x0040);
+ stw(p + 1, s->cylinders);
+ stw(p + 3, s->heads);
+ stw(p + 4, 512 * s->sectors); /* sectors */
+ stw(p + 5, 512); /* sector size */
+ stw(p + 6, s->sectors);
+ stw(p + 20, 3); /* buffer type */
+ stw(p + 21, 512); /* cache size in sectors */
+ stw(p + 22, 4); /* ecc bytes */
+ padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
+#if MAX_MULT_SECTORS > 1
+ stw(p + 47, MAX_MULT_SECTORS);
+#endif
+ stw(p + 48, 1); /* dword I/O */
+ stw(p + 49, 1 << 9); /* LBA supported, no DMA */
+ stw(p + 51, 0x200); /* PIO transfer cycle */
+ stw(p + 52, 0x200); /* DMA transfer cycle */
+ stw(p + 54, s->cylinders);
+ stw(p + 55, s->heads);
+ stw(p + 56, s->sectors);
+ oldsize = s->cylinders * s->heads * s->sectors;
+ stw(p + 57, oldsize);
+ stw(p + 58, oldsize >> 16);
+ if (s->mult_sectors)
+ stw(p + 59, 0x100 | s->mult_sectors);
+ stw(p + 60, s->nb_sectors);
+ stw(p + 61, s->nb_sectors >> 16);
+ stw(p + 80, (1 << 1) | (1 << 2));
+ stw(p + 82, (1 << 14));
+ stw(p + 83, (1 << 14));
+ stw(p + 84, (1 << 14));
+ stw(p + 85, (1 << 14));
+ stw(p + 86, 0);
+ stw(p + 87, (1 << 14));
+}
+
+static inline void ide_abort_command(IDEState *s)
+{
+ s->status = READY_STAT | ERR_STAT;
+ s->error = ABRT_ERR;
+}
+
+static inline void ide_set_irq(IDEState *s)
+{
+ if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
+ pic_set_irq(s->irq, 1);
+ }
+}
-static void host_alarm_handler(int host_signum, siginfo_t *info,
- void *puc)
+/* prepare data transfer and tell what to do after */
+static void ide_transfer_start(IDEState *s, int size,
+ EndTransferFunc *end_transfer_func)
{
- /* NOTE: since usually the OS asks a 100 Hz clock, there can be
- some drift between cpu_get_ticks() and the interrupt time. So
- we queue some interrupts to avoid missing some */
- timer_irq_count += pit_get_out_edges(&pit_channels[0]);
- if (timer_irq_count) {
- if (timer_irq_count > 2)
- timer_irq_count = 2;
- timer_irq_count--;
- /* just exit from the cpu to have a chance to handle timers */
- cpu_x86_interrupt(global_env);
- timer_irq_pending = 1;
- }
+ s->end_transfer_func = end_transfer_func;
+ s->data_ptr = s->io_buffer;
+ s->data_end = s->io_buffer + size;
+ s->status |= DRQ_STAT;
}
-/* main execution loop */
+static void ide_transfer_stop(IDEState *s)
+{
+ s->end_transfer_func = ide_transfer_stop;
+ s->data_ptr = s->io_buffer;
+ s->data_end = s->io_buffer;
+ s->status &= ~DRQ_STAT;
+}
-CPUState *cpu_gdbstub_get_env(void *opaque)
+static int64_t ide_get_sector(IDEState *s)
{
- return global_env;
+ int64_t sector_num;
+ if (s->select & 0x40) {
+ /* lba */
+ sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
+ (s->lcyl << 8) | s->sector;
+ } else {
+ sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
+ (s->select & 0x0f) * s->sectors +
+ (s->sector - 1);
+ }
+ return sector_num;
}
-void main_loop(void *opaque)
+static void ide_set_sector(IDEState *s, int64_t sector_num)
{
- struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
- int ret, n, timeout;
- uint8_t ch;
- CPUState *env = global_env;
+ unsigned int cyl, r;
+ if (s->select & 0x40) {
+ s->select = (s->select & 0xf0) | (sector_num >> 24);
+ s->hcyl = (sector_num >> 16);
+ s->lcyl = (sector_num >> 8);
+ s->sector = (sector_num);
+ } else {
+ cyl = sector_num / (s->heads * s->sectors);
+ r = sector_num % (s->heads * s->sectors);
+ s->hcyl = cyl >> 8;
+ s->lcyl = cyl;
+ s->select = (s->select & 0xf0) | (r / s->sectors);
+ s->sector = (r % s->sectors) + 1;
+ }
+}
- for(;;) {
+static void ide_sector_read(IDEState *s)
+{
+ int64_t sector_num;
+ int ret, n;
- ret = cpu_x86_exec(env);
+ s->status = READY_STAT | SEEK_STAT;
+ sector_num = ide_get_sector(s);
+ n = s->nsector;
+ if (n == 0) {
+ /* no more sector to read from disk */
+ ide_transfer_stop(s);
+ } else {
+#if defined(DEBUG_IDE)
+ printf("read sector=%Ld\n", sector_num);
+#endif
+ if (n > s->req_nb_sectors)
+ n = s->req_nb_sectors;
+ ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
+ ide_transfer_start(s, 512 * n, ide_sector_read);
+ ide_set_irq(s);
+ ide_set_sector(s, sector_num + n);
+ s->nsector -= n;
+ }
+}
- /* if hlt instruction, we wait until the next IRQ */
- if (ret == EXCP_HLT)
- timeout = 10;
- else
- timeout = 0;
- /* poll any events */
- serial_ufd = NULL;
- pf = ufds;
- if (!(serial_ports[0].lsr & UART_LSR_DR)) {
- serial_ufd = pf;
- pf->fd = 0;
- pf->events = POLLIN;
- pf++;
- }
- net_ufd = NULL;
- if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
- net_ufd = pf;
- pf->fd = net_fd;
- pf->events = POLLIN;
- pf++;
- }
- gdb_ufd = NULL;
- if (gdbstub_fd > 0) {
- gdb_ufd = pf;
- pf->fd = gdbstub_fd;
- pf->events = POLLIN;
- pf++;
- }
+static void ide_sector_write(IDEState *s)
+{
+ int64_t sector_num;
+ int ret, n, n1;
- ret = poll(ufds, pf - ufds, timeout);
- if (ret > 0) {
- if (serial_ufd && (serial_ufd->revents & POLLIN)) {
- n = read(0, &ch, 1);
- if (n == 1) {
- serial_received_byte(&serial_ports[0], ch);
- }
- }
- if (net_ufd && (net_ufd->revents & POLLIN)) {
- uint8_t buf[MAX_ETH_FRAME_SIZE];
+ s->status = READY_STAT | SEEK_STAT;
+ sector_num = ide_get_sector(s);
+#if defined(DEBUG_IDE)
+ printf("write sector=%Ld\n", sector_num);
+#endif
+ n = s->nsector;
+ if (n > s->req_nb_sectors)
+ n = s->req_nb_sectors;
+ ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
+ s->nsector -= n;
+ if (s->nsector == 0) {
+ /* no more sector to write */
+ ide_transfer_stop(s);
+ } else {
+ n1 = s->nsector;
+ if (n1 > s->req_nb_sectors)
+ n1 = s->req_nb_sectors;
+ ide_transfer_start(s, 512 * n1, ide_sector_write);
+ }
+ ide_set_sector(s, sector_num + n);
+ ide_set_irq(s);
+}
- n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
- if (n > 0) {
- if (n < 60) {
- memset(buf + n, 0, 60 - n);
- n = 60;
- }
- ne2000_receive(&ne2000_state, buf, n);
- }
- }
- if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
- uint8_t buf[1];
- /* stop emulation if requested by gdb */
- n = read(gdbstub_fd, buf, 1);
- if (n == 1)
- break;
- }
- }
+void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ int unit, n;
- /* timer IRQ */
+ addr &= 7;
+#ifdef DEBUG_IDE
+ printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
+#endif
+ switch(addr) {
+ case 0:
+ break;
+ case 1:
+ s->feature = val;
+ break;
+ case 2:
+ if (val == 0)
+ val = 256;
+ s->nsector = val;
+ break;
+ case 3:
+ s->sector = val;
+ break;
+ case 4:
+ s->lcyl = val;
+ break;
+ case 5:
+ s->hcyl = val;
+ break;
+ case 6:
+ /* select drive */
+ unit = (val >> 4) & 1;
+ s = &ide_state[unit];
+ ide_state[0].cur_drive = s;
+ s->select = val;
+ break;
+ default:
+ case 7:
+ /* command */
+#if defined(DEBUG_IDE)
+ printf("ide: CMD=%02x\n", val);
+#endif
+ switch(val) {
+ case WIN_PIDENTIFY:
+ case WIN_IDENTIFY:
+ if (s->bs) {
+ ide_identify(s);
+ s->status = READY_STAT;
+ ide_transfer_start(s, 512, ide_transfer_stop);
+ } else {
+ ide_abort_command(s);
+ }
+ ide_set_irq(s);
+ break;
+ case WIN_SPECIFY:
+ case WIN_RECAL:
+ s->status = READY_STAT;
+ ide_set_irq(s);
+ break;
+ case WIN_SETMULT:
+ if (s->nsector > MAX_MULT_SECTORS ||
+ s->nsector == 0 ||
+ (s->nsector & (s->nsector - 1)) != 0) {
+ ide_abort_command(s);
+ } else {
+ s->mult_sectors = s->nsector;
+ s->status = READY_STAT;
+ }
+ ide_set_irq(s);
+ break;
+ case WIN_READ:
+ case WIN_READ_ONCE:
+ s->req_nb_sectors = 1;
+ ide_sector_read(s);
+ break;
+ case WIN_WRITE:
+ case WIN_WRITE_ONCE:
+ s->status = SEEK_STAT;
+ s->req_nb_sectors = 1;
+ ide_transfer_start(s, 512, ide_sector_write);
+ break;
+ case WIN_MULTREAD:
+ if (!s->mult_sectors)
+ goto abort_cmd;
+ s->req_nb_sectors = s->mult_sectors;
+ ide_sector_read(s);
+ break;
+ case WIN_MULTWRITE:
+ if (!s->mult_sectors)
+ goto abort_cmd;
+ s->status = SEEK_STAT;
+ s->req_nb_sectors = s->mult_sectors;
+ n = s->nsector;
+ if (n > s->req_nb_sectors)
+ n = s->req_nb_sectors;
+ ide_transfer_start(s, 512 * n, ide_sector_write);
+ break;
+ case WIN_READ_NATIVE_MAX:
+ ide_set_sector(s, s->nb_sectors - 1);
+ s->status = READY_STAT;
+ ide_set_irq(s);
+ break;
+ default:
+ abort_cmd:
+ ide_abort_command(s);
+ ide_set_irq(s);
+ break;
+ }
+ }
+}
+
+uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ int ret;
+
+ addr &= 7;
+ switch(addr) {
+ case 0:
+ ret = 0xff;
+ break;
+ case 1:
+ ret = s->error;
+ break;
+ case 2:
+ ret = s->nsector & 0xff;
+ break;
+ case 3:
+ ret = s->sector;
+ break;
+ case 4:
+ ret = s->lcyl;
+ break;
+ case 5:
+ ret = s->hcyl;
+ break;
+ case 6:
+ ret = s->select;
+ break;
+ default:
+ case 7:
+ ret = s->status;
+ pic_set_irq(s->irq, 0);
+ break;
+ }
+#ifdef DEBUG_IDE
+ printf("ide: read addr=0x%x val=%02x\n", addr, ret);
+#endif
+ return ret;
+}
+
+uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ int ret;
+ ret = s->status;
+#ifdef DEBUG_IDE
+ printf("ide: read status val=%02x\n", ret);
+#endif
+ return ret;
+}
+
+void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ IDEState *s;
+ int i;
+
+#ifdef DEBUG_IDE
+ printf("ide: write control val=%02x\n", val);
+#endif
+ /* common for both drives */
+ if (!(ide_state[0].cmd & IDE_CMD_RESET) &&
+ (val & IDE_CMD_RESET)) {
+ /* reset low to high */
+ for(i = 0;i < 2; i++) {
+ s = &ide_state[i];
+ s->status = BUSY_STAT | SEEK_STAT;
+ s->error = 0x01;
+ }
+ } else if ((ide_state[0].cmd & IDE_CMD_RESET) &&
+ !(val & IDE_CMD_RESET)) {
+ /* high to low */
+ for(i = 0;i < 2; i++) {
+ s = &ide_state[i];
+ s->status = READY_STAT;
+ /* set hard disk drive ID */
+ s->select &= 0xf0; /* clear head */
+ s->nsector = 1;
+ s->sector = 1;
+ if (s->nb_sectors == 0) {
+ /* no disk present */
+ s->lcyl = 0x12;
+ s->hcyl = 0x34;
+ } else {
+ s->lcyl = 0;
+ s->hcyl = 0;
+ }
+ }
+ }
+
+ ide_state[0].cmd = val;
+}
+
+void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ uint8_t *p;
+
+ p = s->data_ptr;
+ *(uint16_t *)p = tswap16(val);
+ p += 2;
+ s->data_ptr = p;
+ if (p >= s->data_end)
+ s->end_transfer_func(s);
+}
+
+uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ uint8_t *p;
+ int ret;
+
+ p = s->data_ptr;
+ ret = tswap16(*(uint16_t *)p);
+ p += 2;
+ s->data_ptr = p;
+ if (p >= s->data_end)
+ s->end_transfer_func(s);
+ return ret;
+}
+
+void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ uint8_t *p;
+
+ p = s->data_ptr;
+ *(uint32_t *)p = tswap32(val);
+ p += 4;
+ s->data_ptr = p;
+ if (p >= s->data_end)
+ s->end_transfer_func(s);
+}
+
+uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
+{
+ IDEState *s = ide_state[0].cur_drive;
+ uint8_t *p;
+ int ret;
+
+ p = s->data_ptr;
+ ret = tswap32(*(uint32_t *)p);
+ p += 4;
+ s->data_ptr = p;
+ if (p >= s->data_end)
+ s->end_transfer_func(s);
+ return ret;
+}
+
+void ide_reset(IDEState *s)
+{
+ s->mult_sectors = MAX_MULT_SECTORS;
+ s->status = READY_STAT;
+ s->cur_drive = s;
+ s->select = 0xa0;
+}
+
+void ide_init(void)
+{
+ IDEState *s;
+ int i, cylinders;
+ int64_t nb_sectors;
+
+ for(i = 0; i < MAX_DISKS; i++) {
+ s = &ide_state[i];
+ s->bs = bs_table[i];
+ if (s->bs) {
+ bdrv_get_geometry(s->bs, &nb_sectors);
+ if (s->cylinders == 0) {
+ /* if no geometry, use a LBA compatible one */
+ cylinders = nb_sectors / (16 * 63);
+ if (cylinders > 16383)
+ cylinders = 16383;
+ else if (cylinders < 2)
+ cylinders = 2;
+ s->cylinders = cylinders;
+ s->heads = 16;
+ s->sectors = 63;
+ }
+ s->nb_sectors = nb_sectors;
+ }
+ s->irq = 14;
+ ide_reset(s);
+ }
+ register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
+ register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
+ register_ioport_read(0x3f6, 1, ide_status_read, 1);
+ register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
+
+ /* data ports */
+ register_ioport_write(0x1f0, 2, ide_data_writew, 2);
+ register_ioport_read(0x1f0, 2, ide_data_readw, 2);
+ register_ioport_write(0x1f0, 4, ide_data_writel, 4);
+ register_ioport_read(0x1f0, 4, ide_data_readl, 4);
+}
+
+/***********************************************************/
+/* keyboard emulation */
+
+/* Keyboard Controller Commands */
+#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
+#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
+#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
+#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
+#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
+#define KBD_CCMD_READ_INPORT 0xC0 /* read input port */
+#define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */
+#define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */
+#define KBD_CCMD_WRITE_OBUF 0xD2
+#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
+ initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
+#define KBD_CCMD_ENABLE_A20 0xDD
+#define KBD_CCMD_DISABLE_A20 0xDF
+#define KBD_CCMD_RESET 0xFE
+
+/* Keyboard Commands */
+#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
+#define KBD_CMD_ECHO 0xEE
+#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
+#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
+#define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
+#define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
+#define KBD_CMD_RESET 0xFF /* Reset */
+
+/* Keyboard Replies */
+#define KBD_REPLY_POR 0xAA /* Power on reset */
+#define KBD_REPLY_ACK 0xFA /* Command ACK */
+#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
+
+/* Status Register Bits */
+#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
+#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
+#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
+#define KBD_STAT_PERR 0x80 /* Parity error */
+
+/* Controller Mode Register Bits */
+#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 0x04 /* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
+#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
+#define KBD_MODE_RFU 0x80
+
+/* Mouse Commands */
+#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
+#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
+#define AUX_SET_RES 0xE8 /* Set resolution */
+#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
+#define AUX_SET_STREAM 0xEA /* Set stream mode */
+#define AUX_POLL 0xEB /* Poll */
+#define AUX_RESET_WRAP 0xEC /* Reset wrap mode */
+#define AUX_SET_WRAP 0xEE /* Set wrap mode */
+#define AUX_SET_REMOTE 0xF0 /* Set remote mode */
+#define AUX_GET_TYPE 0xF2 /* Get type */
+#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
+#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
+#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
+#define AUX_SET_DEFAULT 0xF6
+#define AUX_RESET 0xFF /* Reset aux device */
+#define AUX_ACK 0xFA /* Command byte ACK. */
+
+#define MOUSE_STATUS_REMOTE 0x40
+#define MOUSE_STATUS_ENABLED 0x20
+#define MOUSE_STATUS_SCALE21 0x10
+
+#define KBD_QUEUE_SIZE 256
+
+typedef struct {
+ uint8_t data[KBD_QUEUE_SIZE];
+ int rptr, wptr, count;
+} KBDQueue;
+
+typedef struct KBDState {
+ KBDQueue queues[2];
+ uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
+ uint8_t status;
+ uint8_t mode;
+ /* keyboard state */
+ int kbd_write_cmd;
+ int scan_enabled;
+ /* mouse state */
+ int mouse_write_cmd;
+ uint8_t mouse_status;
+ uint8_t mouse_resolution;
+ uint8_t mouse_sample_rate;
+ uint8_t mouse_wrap;
+ uint8_t mouse_type; /* 0 = PS2, 3 = IMPS/2, 4 = IMEX */
+ uint8_t mouse_detect_state;
+ int mouse_dx; /* current values, needed for 'poll' mode */
+ int mouse_dy;
+ int mouse_dz;
+ uint8_t mouse_buttons;
+} KBDState;
+
+KBDState kbd_state;
+int reset_requested;
+int a20_enabled;
+
+/* update irq and KBD_STAT_[MOUSE_]OBF */
+static void kbd_update_irq(KBDState *s)
+{
+ int irq12_level, irq1_level;
+
+ irq1_level = 0;
+ irq12_level = 0;
+ s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF);
+ if (s->queues[0].count != 0 ||
+ s->queues[1].count != 0) {
+ s->status |= KBD_STAT_OBF;
+ if (s->queues[1].count != 0) {
+ s->status |= KBD_STAT_MOUSE_OBF;
+ if (s->mode & KBD_MODE_MOUSE_INT)
+ irq12_level = 1;
+ } else {
+ if (s->mode & KBD_MODE_KBD_INT)
+ irq1_level = 1;
+ }
+ }
+ pic_set_irq(1, irq1_level);
+ pic_set_irq(12, irq12_level);
+}
+
+static void kbd_queue(KBDState *s, int b, int aux)
+{
+ KBDQueue *q = &kbd_state.queues[aux];
+
+#if defined(DEBUG_MOUSE) || defined(DEBUG_KBD)
+ if (aux)
+ printf("mouse event: 0x%02x\n", b);
+#ifdef DEBUG_KBD
+ else
+ printf("kbd event: 0x%02x\n", b);
+#endif
+#endif
+ if (q->count >= KBD_QUEUE_SIZE)
+ return;
+ q->data[q->wptr] = b;
+ if (++q->wptr == KBD_QUEUE_SIZE)
+ q->wptr = 0;
+ q->count++;
+ kbd_update_irq(s);
+}
+
+void kbd_put_keycode(int keycode)
+{
+ KBDState *s = &kbd_state;
+ kbd_queue(s, keycode, 0);
+}
+
+uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
+{
+ KBDState *s = &kbd_state;
+ int val;
+ val = s->status;
+#if defined(DEBUG_KBD) && 0
+ printf("kbd: read status=0x%02x\n", val);
+#endif
+ return val;
+}
+
+void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ KBDState *s = &kbd_state;
+
+#ifdef DEBUG_KBD
+ printf("kbd: write cmd=0x%02x\n", val);
+#endif
+ switch(val) {
+ case KBD_CCMD_READ_MODE:
+ kbd_queue(s, s->mode, 0);
+ break;
+ case KBD_CCMD_WRITE_MODE:
+ case KBD_CCMD_WRITE_OBUF:
+ case KBD_CCMD_WRITE_AUX_OBUF:
+ case KBD_CCMD_WRITE_MOUSE:
+ case KBD_CCMD_WRITE_OUTPORT:
+ s->write_cmd = val;
+ break;
+ case KBD_CCMD_MOUSE_DISABLE:
+ s->mode |= KBD_MODE_DISABLE_MOUSE;
+ break;
+ case KBD_CCMD_MOUSE_ENABLE:
+ s->mode &= ~KBD_MODE_DISABLE_MOUSE;
+ break;
+ case KBD_CCMD_TEST_MOUSE:
+ kbd_queue(s, 0x00, 0);
+ break;
+ case KBD_CCMD_SELF_TEST:
+ s->status |= KBD_STAT_SELFTEST;
+ kbd_queue(s, 0x55, 0);
+ break;
+ case KBD_CCMD_KBD_TEST:
+ kbd_queue(s, 0x00, 0);
+ break;
+ case KBD_CCMD_KBD_DISABLE:
+ s->mode |= KBD_MODE_DISABLE_KBD;
+ break;
+ case KBD_CCMD_KBD_ENABLE:
+ s->mode &= ~KBD_MODE_DISABLE_KBD;
+ break;
+ case KBD_CCMD_READ_INPORT:
+ kbd_queue(s, 0x00, 0);
+ break;
+ case KBD_CCMD_READ_OUTPORT:
+ /* XXX: check that */
+ val = 0x01 | (a20_enabled << 1);
+ if (s->status & KBD_STAT_OBF)
+ val |= 0x10;
+ if (s->status & KBD_STAT_MOUSE_OBF)
+ val |= 0x20;
+ kbd_queue(s, val, 0);
+ break;
+ case KBD_CCMD_ENABLE_A20:
+ a20_enabled = 1;
+ break;
+ case KBD_CCMD_DISABLE_A20:
+ a20_enabled = 0;
+ break;
+ case KBD_CCMD_RESET:
+ reset_requested = 1;
+ cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
+ break;
+ default:
+ fprintf(stderr, "vl: unsupported keyboard cmd=0x%02x\n", val);
+ break;
+ }
+}
+
+uint32_t kbd_read_data(CPUX86State *env, uint32_t addr)
+{
+ KBDState *s = &kbd_state;
+ KBDQueue *q;
+ int val;
+
+ q = &s->queues[0]; /* first check KBD data */
+ if (q->count == 0)
+ q = &s->queues[1]; /* then check AUX data */
+ if (q->count == 0) {
+ /* XXX: return something else ? */
+ val = 0;
+ } else {
+ val = q->data[q->rptr];
+ if (++q->rptr == KBD_QUEUE_SIZE)
+ q->rptr = 0;
+ q->count--;
+ /* reading deasserts IRQ */
+ if (q == &s->queues[0])
+ pic_set_irq(1, 0);
+ else
+ pic_set_irq(12, 0);
+ }
+ /* reassert IRQs if data left */
+ kbd_update_irq(s);
+#ifdef DEBUG_KBD
+ printf("kbd: read data=0x%02x\n", val);
+#endif
+ return val;
+}
+
+static void kbd_reset_keyboard(KBDState *s)
+{
+ s->scan_enabled = 1;
+}
+
+static void kbd_write_keyboard(KBDState *s, int val)
+{
+ switch(s->kbd_write_cmd) {
+ default:
+ case -1:
+ switch(val) {
+ case 0x00:
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ break;
+ case 0x05:
+ kbd_queue(s, KBD_REPLY_RESEND, 0);
+ break;
+ case KBD_CMD_ECHO:
+ kbd_queue(s, KBD_CMD_ECHO, 0);
+ break;
+ case KBD_CMD_ENABLE:
+ s->scan_enabled = 1;
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ break;
+ case KBD_CMD_SET_LEDS:
+ case KBD_CMD_SET_RATE:
+ s->kbd_write_cmd = val;
+ break;
+ case KBD_CMD_RESET_DISABLE:
+ kbd_reset_keyboard(s);
+ s->scan_enabled = 0;
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ break;
+ case KBD_CMD_RESET_ENABLE:
+ kbd_reset_keyboard(s);
+ s->scan_enabled = 1;
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ break;
+ case KBD_CMD_RESET:
+ kbd_reset_keyboard(s);
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ kbd_queue(s, KBD_REPLY_POR, 0);
+ break;
+ default:
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ break;
+ }
+ break;
+ case KBD_CMD_SET_LEDS:
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ s->kbd_write_cmd = -1;
+ break;
+ case KBD_CMD_SET_RATE:
+ kbd_queue(s, KBD_REPLY_ACK, 0);
+ s->kbd_write_cmd = -1;
+ break;
+ }
+}
+
+static void kbd_mouse_send_packet(KBDState *s)
+{
+ unsigned int b;
+ int dx1, dy1, dz1;
+
+ dx1 = s->mouse_dx;
+ dy1 = s->mouse_dy;
+ dz1 = s->mouse_dz;
+ /* XXX: increase range to 8 bits ? */
+ if (dx1 > 127)
+ dx1 = 127;
+ else if (dx1 < -127)
+ dx1 = -127;
+ if (dy1 > 127)
+ dy1 = 127;
+ else if (dy1 < -127)
+ dy1 = -127;
+ b = 0x08 | ((dx1 < 0) << 4) | ((dy1 < 0) << 5) | (s->mouse_buttons & 0x07);
+ kbd_queue(s, b, 1);
+ kbd_queue(s, dx1 & 0xff, 1);
+ kbd_queue(s, dy1 & 0xff, 1);
+ /* extra byte for IMPS/2 or IMEX */
+ switch(s->mouse_type) {
+ default:
+ break;
+ case 3:
+ if (dz1 > 127)
+ dz1 = 127;
+ else if (dz1 < -127)
+ dz1 = -127;
+ kbd_queue(s, dz1 & 0xff, 1);
+ break;
+ case 4:
+ if (dz1 > 7)
+ dz1 = 7;
+ else if (dz1 < -7)
+ dz1 = -7;
+ b = (dz1 & 0x0f) | ((s->mouse_buttons & 0x18) << 1);
+ kbd_queue(s, b, 1);
+ break;
+ }
+
+ /* update deltas */
+ s->mouse_dx -= dx1;
+ s->mouse_dy -= dy1;
+ s->mouse_dz -= dz1;
+}
+
+void kbd_mouse_event(int dx, int dy, int dz, int buttons_state)
+{
+ KBDState *s = &kbd_state;
+
+ /* check if deltas are recorded when disabled */
+ if (!(s->mouse_status & MOUSE_STATUS_ENABLED))
+ return;
+
+ s->mouse_dx += dx;
+ s->mouse_dy -= dy;
+ s->mouse_dz += dz;
+ s->mouse_buttons = buttons_state;
+
+ if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
+ (s->queues[1].count < (KBD_QUEUE_SIZE - 16))) {
+ for(;;) {
+ /* if not remote, send event. Multiple events are sent if
+ too big deltas */
+ kbd_mouse_send_packet(s);
+ if (s->mouse_dx == 0 && s->mouse_dy == 0 && s->mouse_dz == 0)
+ break;
+ }
+ }
+}
+
+static void kbd_write_mouse(KBDState *s, int val)
+{
+#ifdef DEBUG_MOUSE
+ printf("kbd: write mouse 0x%02x\n", val);
+#endif
+ switch(s->mouse_write_cmd) {
+ default:
+ case -1:
+ /* mouse command */
+ if (s->mouse_wrap) {
+ if (val == AUX_RESET_WRAP) {
+ s->mouse_wrap = 0;
+ kbd_queue(s, AUX_ACK, 1);
+ return;
+ } else if (val != AUX_RESET) {
+ kbd_queue(s, val, 1);
+ return;
+ }
+ }
+ switch(val) {
+ case AUX_SET_SCALE11:
+ s->mouse_status &= ~MOUSE_STATUS_SCALE21;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_SET_SCALE21:
+ s->mouse_status |= MOUSE_STATUS_SCALE21;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_SET_STREAM:
+ s->mouse_status &= ~MOUSE_STATUS_REMOTE;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_SET_WRAP:
+ s->mouse_wrap = 1;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_SET_REMOTE:
+ s->mouse_status |= MOUSE_STATUS_REMOTE;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_GET_TYPE:
+ kbd_queue(s, AUX_ACK, 1);
+ kbd_queue(s, s->mouse_type, 1);
+ break;
+ case AUX_SET_RES:
+ case AUX_SET_SAMPLE:
+ s->mouse_write_cmd = val;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_GET_SCALE:
+ kbd_queue(s, AUX_ACK, 1);
+ kbd_queue(s, s->mouse_status, 1);
+ kbd_queue(s, s->mouse_resolution, 1);
+ kbd_queue(s, s->mouse_sample_rate, 1);
+ break;
+ case AUX_POLL:
+ kbd_queue(s, AUX_ACK, 1);
+ kbd_mouse_send_packet(s);
+ break;
+ case AUX_ENABLE_DEV:
+ s->mouse_status |= MOUSE_STATUS_ENABLED;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_DISABLE_DEV:
+ s->mouse_status &= ~MOUSE_STATUS_ENABLED;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_SET_DEFAULT:
+ s->mouse_sample_rate = 100;
+ s->mouse_resolution = 2;
+ s->mouse_status = 0;
+ kbd_queue(s, AUX_ACK, 1);
+ break;
+ case AUX_RESET:
+ s->mouse_sample_rate = 100;
+ s->mouse_resolution = 2;
+ s->mouse_status = 0;
+ kbd_queue(s, AUX_ACK, 1);
+ kbd_queue(s, 0xaa, 1);
+ kbd_queue(s, s->mouse_type, 1);
+ break;
+ default:
+ break;
+ }
+ break;
+ case AUX_SET_SAMPLE:
+ s->mouse_sample_rate = val;
+#if 0
+ /* detect IMPS/2 or IMEX */
+ switch(s->mouse_detect_state) {
+ default:
+ case 0:
+ if (val == 200)
+ s->mouse_detect_state = 1;
+ break;
+ case 1:
+ if (val == 100)
+ s->mouse_detect_state = 2;
+ else if (val == 200)
+ s->mouse_detect_state = 3;
+ else
+ s->mouse_detect_state = 0;
+ break;
+ case 2:
+ if (val == 80)
+ s->mouse_type = 3; /* IMPS/2 */
+ s->mouse_detect_state = 0;
+ break;
+ case 3:
+ if (val == 80)
+ s->mouse_type = 4; /* IMEX */
+ s->mouse_detect_state = 0;
+ break;
+ }
+#endif
+ kbd_queue(s, AUX_ACK, 1);
+ s->mouse_write_cmd = -1;
+ break;
+ case AUX_SET_RES:
+ s->mouse_resolution = val;
+ kbd_queue(s, AUX_ACK, 1);
+ s->mouse_write_cmd = -1;
+ break;
+ }
+}
+
+void kbd_write_data(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ KBDState *s = &kbd_state;
+
+#ifdef DEBUG_KBD
+ printf("kbd: write data=0x%02x\n", val);
+#endif
+
+ switch(s->write_cmd) {
+ case 0:
+ kbd_write_keyboard(s, val);
+ break;
+ case KBD_CCMD_WRITE_MODE:
+ s->mode = val;
+ kbd_update_irq(s);
+ break;
+ case KBD_CCMD_WRITE_OBUF:
+ kbd_queue(s, val, 0);
+ break;
+ case KBD_CCMD_WRITE_AUX_OBUF:
+ kbd_queue(s, val, 1);
+ break;
+ case KBD_CCMD_WRITE_OUTPORT:
+ a20_enabled = (val >> 1) & 1;
+ if (!(val & 1)) {
+ reset_requested = 1;
+ cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
+ }
+ break;
+ case KBD_CCMD_WRITE_MOUSE:
+ kbd_write_mouse(s, val);
+ break;
+ default:
+ break;
+ }
+ s->write_cmd = 0;
+}
+
+void kbd_reset(KBDState *s)
+{
+ KBDQueue *q;
+ int i;
+
+ s->kbd_write_cmd = -1;
+ s->mouse_write_cmd = -1;
+ s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT;
+ s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED;
+ for(i = 0; i < 2; i++) {
+ q = &s->queues[i];
+ q->rptr = 0;
+ q->wptr = 0;
+ q->count = 0;
+ }
+}
+
+void kbd_init(void)
+{
+ kbd_reset(&kbd_state);
+ register_ioport_read(0x60, 1, kbd_read_data, 1);
+ register_ioport_write(0x60, 1, kbd_write_data, 1);
+ register_ioport_read(0x64, 1, kbd_read_status, 1);
+ register_ioport_write(0x64, 1, kbd_write_command, 1);
+}
+
+/***********************************************************/
+/* Bochs BIOS debug ports */
+
+void bochs_bios_write(CPUX86State *env, uint32_t addr, uint32_t val)
+{
+ switch(addr) {
+ /* Bochs BIOS messages */
+ case 0x400:
+ case 0x401:
+ fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
+ exit(1);
+ case 0x402:
+ case 0x403:
+#ifdef DEBUG_BIOS
+ fprintf(stderr, "%c", val);
+#endif
+ break;
+
+ /* LGPL'ed VGA BIOS messages */
+ case 0x501:
+ case 0x502:
+ fprintf(stderr, "VGA BIOS panic, line %d\n", val);
+ exit(1);
+ case 0x500:
+ case 0x503:
+#ifdef DEBUG_BIOS
+ fprintf(stderr, "%c", val);
+#endif
+ break;
+ }
+}
+
+void bochs_bios_init(void)
+{
+ register_ioport_write(0x400, 1, bochs_bios_write, 2);
+ register_ioport_write(0x401, 1, bochs_bios_write, 2);
+ register_ioport_write(0x402, 1, bochs_bios_write, 1);
+ register_ioport_write(0x403, 1, bochs_bios_write, 1);
+
+ register_ioport_write(0x501, 1, bochs_bios_write, 2);
+ register_ioport_write(0x502, 1, bochs_bios_write, 2);
+ register_ioport_write(0x500, 1, bochs_bios_write, 1);
+ register_ioport_write(0x503, 1, bochs_bios_write, 1);
+}
+
+/***********************************************************/
+/* dumb display */
+
+/* init terminal so that we can grab keys */
+static struct termios oldtty;
+
+static void term_exit(void)
+{
+ tcsetattr (0, TCSANOW, &oldtty);
+}
+
+static void term_init(void)
+{
+ struct termios tty;
+
+ tcgetattr (0, &tty);
+ oldtty = tty;
+
+ tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
+ |INLCR|IGNCR|ICRNL|IXON);
+ tty.c_oflag |= OPOST;
+ tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
+ tty.c_cflag &= ~(CSIZE|PARENB);
+ tty.c_cflag |= CS8;
+ tty.c_cc[VMIN] = 1;
+ tty.c_cc[VTIME] = 0;
+
+ tcsetattr (0, TCSANOW, &tty);
+
+ atexit(term_exit);
+
+ fcntl(0, F_SETFL, O_NONBLOCK);
+}
+
+static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
+{
+}
+
+static void dumb_resize(DisplayState *ds, int w, int h)
+{
+}
+
+static void dumb_refresh(DisplayState *ds)
+{
+ vga_update_display();
+}
+
+void dumb_display_init(DisplayState *ds)
+{
+ ds->data = NULL;
+ ds->linesize = 0;
+ ds->depth = 0;
+ ds->dpy_update = dumb_update;
+ ds->dpy_resize = dumb_resize;
+ ds->dpy_refresh = dumb_refresh;
+}
+
+/***********************************************************/
+/* cpu signal handler */
+static void host_segv_handler(int host_signum, siginfo_t *info,
+ void *puc)
+{
+ if (cpu_signal_handler(host_signum, info, puc))
+ return;
+ term_exit();
+ abort();
+}
+
+static int timer_irq_pending;
+static int timer_irq_count;
+
+static int timer_ms;
+static int gui_refresh_pending, gui_refresh_count;
+
+static void host_alarm_handler(int host_signum, siginfo_t *info,
+ void *puc)
+{
+ /* NOTE: since usually the OS asks a 100 Hz clock, there can be
+ some drift between cpu_get_ticks() and the interrupt time. So
+ we queue some interrupts to avoid missing some */
+ timer_irq_count += pit_get_out_edges(&pit_channels[0]);
+ if (timer_irq_count) {
+ if (timer_irq_count > 2)
+ timer_irq_count = 2;
+ timer_irq_count--;
+ timer_irq_pending = 1;
+ }
+ gui_refresh_count += timer_ms;
+ if (gui_refresh_count >= GUI_REFRESH_INTERVAL) {
+ gui_refresh_count = 0;
+ gui_refresh_pending = 1;
+ }
+
+ if (gui_refresh_pending || timer_irq_pending) {
+ /* just exit from the cpu to have a chance to handle timers */
+ cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
+ }
+}
+
+unsigned long mmap_addr = PHYS_RAM_BASE;
+
+void *get_mmap_addr(unsigned long size)
+{
+ unsigned long addr;
+ addr = mmap_addr;
+ mmap_addr += ((size + 4095) & ~4095) + 4096;
+ return (void *)addr;
+}
+
+/* main execution loop */
+
+CPUState *cpu_gdbstub_get_env(void *opaque)
+{
+ return global_env;
+}
+
+int main_loop(void *opaque)
+{
+ struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
+ int ret, n, timeout;
+ uint8_t ch;
+ CPUState *env = global_env;
+
+ if (nodisp && !term_inited) {
+ /* initialize terminal only there so that the user has a
+ chance to stop QEMU with Ctrl-C before the gdb connection
+ is launched */
+ term_inited = 1;
+ term_init();
+ }
+
+ for(;;) {
+ ret = cpu_x86_exec(env);
+ if (reset_requested)
+ break;
+ if (ret == EXCP_DEBUG)
+ return EXCP_DEBUG;
+ /* if hlt instruction, we wait until the next IRQ */
+ if (ret == EXCP_HLT)
+ timeout = 10;
+ else
+ timeout = 0;
+ /* poll any events */
+ serial_ufd = NULL;
+ pf = ufds;
+ if (!(serial_ports[0].lsr & UART_LSR_DR)) {
+ serial_ufd = pf;
+ pf->fd = 0;
+ pf->events = POLLIN;
+ pf++;
+ }
+ net_ufd = NULL;
+ if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
+ net_ufd = pf;
+ pf->fd = net_fd;
+ pf->events = POLLIN;
+ pf++;
+ }
+ gdb_ufd = NULL;
+ if (gdbstub_fd > 0) {
+ gdb_ufd = pf;
+ pf->fd = gdbstub_fd;
+ pf->events = POLLIN;
+ pf++;
+ }
+
+ ret = poll(ufds, pf - ufds, timeout);
+ if (ret > 0) {
+ if (serial_ufd && (serial_ufd->revents & POLLIN)) {
+ n = read(0, &ch, 1);
+ if (n == 1) {
+ serial_received_byte(&serial_ports[0], ch);
+ }
+ }
+ if (net_ufd && (net_ufd->revents & POLLIN)) {
+ uint8_t buf[MAX_ETH_FRAME_SIZE];
+
+ n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
+ if (n > 0) {
+ if (n < 60) {
+ memset(buf + n, 0, 60 - n);
+ n = 60;
+ }
+ ne2000_receive(&ne2000_state, buf, n);
+ }
+ }
+ if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
+ uint8_t buf[1];
+ /* stop emulation if requested by gdb */
+ n = read(gdbstub_fd, buf, 1);
+ if (n == 1)
+ break;
+ }
+ }
+
+ /* timer IRQ */
if (timer_irq_pending) {
pic_set_irq(0, 1);
pic_set_irq(0, 0);
timer_irq_pending = 0;
}
- pic_handle_irq();
+ /* VGA */
+ if (gui_refresh_pending) {
+ display_state.dpy_refresh(&display_state);
+ gui_refresh_pending = 0;
+ }
}
+ return EXCP_INTERRUPT;
}
void help(void)
{
printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
- "usage: vl [options] bzImage initrd [kernel parameters...]\n"
+ "usage: vl [options] [bzImage [kernel parameters...]]\n"
"\n"
"'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
"to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
- "'initrd' is an initrd image\n"
- "-m megs set virtual RAM size to megs MB\n"
- "-n script set network init script [default=%s]\n"
- "-s wait gdb connection to port %d\n"
- "-p port change gdb connection port\n"
- "-d output log in /tmp/vl.log\n"
+ "\n"
+ "General options:\n"
+ "-initrd file use 'file' as initial ram disk\n"
+ "-hda file use 'file' as hard disk 0 image\n"
+ "-hdb file use 'file' as hard disk 1 image\n"
+ "-snapshot write to temporary files instead of disk image files\n"
+ "-m megs set virtual RAM size to megs MB\n"
+ "-n script set network init script [default=%s]\n"
+ "\n"
+ "Debug/Expert options:\n"
+ "-s wait gdb connection to port %d\n"
+ "-p port change gdb connection port\n"
+ "-d output log in /tmp/vl.log\n"
+ "-hdachs c,h,s force hard disk 0 geometry for non LBA disk images\n"
+ "-L path set the directory for the BIOS and VGA BIOS\n"
"\n"
"During emulation, use C-a h to get terminal commands:\n",
DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
exit(1);
}
+struct option long_options[] = {
+ { "initrd", 1, NULL, 0, },
+ { "hda", 1, NULL, 0, },
+ { "hdb", 1, NULL, 0, },
+ { "snapshot", 0, NULL, 0, },
+ { "hdachs", 1, NULL, 0, },
+ { "nodisp", 0, NULL, 0, },
+ { NULL, 0, NULL, 0 },
+};
+
int main(int argc, char **argv)
{
- int c, ret, initrd_size, i, use_gdbstub, gdbstub_port;
+ int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
+ int snapshot, linux_boot, total_ram_size;
struct linux_params *params;
struct sigaction act;
struct itimerval itv;
CPUX86State *env;
- const char *tmpdir;
-
+ const char *tmpdir, *initrd_filename;
+ const char *hd_filename[MAX_DISKS];
+ DisplayState *ds = &display_state;
+
/* we never want that malloc() uses mmap() */
mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
-
+ initrd_filename = NULL;
+ for(i = 0; i < MAX_DISKS; i++)
+ hd_filename[i] = NULL;
phys_ram_size = 32 * 1024 * 1024;
+ vga_ram_size = VGA_RAM_SIZE;
pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
use_gdbstub = 0;
gdbstub_port = DEFAULT_GDBSTUB_PORT;
+ snapshot = 0;
+ linux_boot = 0;
+ nodisp = 0;
for(;;) {
- c = getopt(argc, argv, "hm:dn:sp:");
+ c = getopt_long_only(argc, argv, "hm:dn:sp:L:", long_options, &long_index);
if (c == -1)
break;
switch(c) {
+ case 0:
+ switch(long_index) {
+ case 0:
+ initrd_filename = optarg;
+ break;
+ case 1:
+ hd_filename[0] = optarg;
+ break;
+ case 2:
+ hd_filename[1] = optarg;
+ break;
+ case 3:
+ snapshot = 1;
+ break;
+ case 4:
+ {
+ int cyls, heads, secs;
+ const char *p;
+ p = optarg;
+ cyls = strtol(p, (char **)&p, 0);
+ if (*p != ',')
+ goto chs_fail;
+ p++;
+ heads = strtol(p, (char **)&p, 0);
+ if (*p != ',')
+ goto chs_fail;
+ p++;
+ secs = strtol(p, (char **)&p, 0);
+ if (*p != '\0')
+ goto chs_fail;
+ ide_state[0].cylinders = cyls;
+ ide_state[0].heads = heads;
+ ide_state[0].sectors = secs;
+ chs_fail: ;
+ }
+ break;
+ case 5:
+ nodisp = 1;
+ break;
+ }
+ break;
case 'h':
help();
break;
phys_ram_size = atoi(optarg) * 1024 * 1024;
if (phys_ram_size <= 0)
help();
+ if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
+ fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
+ PHYS_RAM_MAX_SIZE / (1024 * 1024));
+ exit(1);
+ }
break;
case 'd':
loglevel = 1;
case 'p':
gdbstub_port = atoi(optarg);
break;
+ case 'L':
+ interp_prefix = optarg;
+ break;
}
}
- if (optind + 1 >= argc)
+
+ linux_boot = (optind < argc);
+
+ if (!linux_boot && hd_filename[0] == '\0')
help();
/* init debug */
+ setvbuf(stdout, NULL, _IOLBF, 0);
if (loglevel) {
logfile = fopen(DEBUG_LOGFILE, "w");
if (!logfile) {
phys_ram_file);
exit(1);
}
- ftruncate(phys_ram_fd, phys_ram_size);
+ total_ram_size = phys_ram_size + vga_ram_size;
+ ftruncate(phys_ram_fd, total_ram_size);
unlink(phys_ram_file);
- phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size,
+ phys_ram_base = mmap(get_mmap_addr(total_ram_size),
+ total_ram_size,
PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
phys_ram_fd, 0);
if (phys_ram_base == MAP_FAILED) {
exit(1);
}
- /* now we can load the kernel */
- ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
- if (ret < 0) {
- fprintf(stderr, "%s: could not load kernel\n", argv[optind]);
- exit(1);
+ /* open the virtual block devices */
+ for(i = 0; i < MAX_DISKS; i++) {
+ if (hd_filename[i]) {
+ bs_table[i] = bdrv_open(hd_filename[i], snapshot);
+ if (!bs_table[i]) {
+ fprintf(stderr, "vl: could not open hard disk image '%s\n",
+ hd_filename[i]);
+ exit(1);
+ }
+ }
}
- /* load initrd */
- initrd_size = load_image(argv[optind + 1], phys_ram_base + INITRD_LOAD_ADDR);
- if (initrd_size < 0) {
- fprintf(stderr, "%s: could not load initrd\n", argv[optind + 1]);
- exit(1);
- }
+ /* init CPU state */
+ env = cpu_init();
+ global_env = env;
+ cpu_single_env = env;
- /* init kernel params */
- params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
- memset(params, 0, sizeof(struct linux_params));
- params->mount_root_rdonly = 0;
- params->cl_magic = 0xA33F;
- params->cl_offset = params->commandline - (uint8_t *)params;
- params->ext_mem_k = (phys_ram_size / 1024) - 1024;
- for(i = optind + 2; i < argc; i++) {
- if (i != optind + 2)
- pstrcat(params->commandline, sizeof(params->commandline), " ");
- pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
- }
- params->loader_type = 0x01;
- if (initrd_size > 0) {
- params->initrd_start = INITRD_LOAD_ADDR;
- params->initrd_size = initrd_size;
+ init_ioports();
+
+ /* allocate RAM */
+ cpu_register_physical_memory(0, phys_ram_size, 0);
+
+ if (linux_boot) {
+ /* now we can load the kernel */
+ ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
+ if (ret < 0) {
+ fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
+ exit(1);
+ }
+
+ /* load initrd */
+ initrd_size = 0;
+ if (initrd_filename) {
+ initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
+ if (initrd_size < 0) {
+ fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
+ initrd_filename);
+ exit(1);
+ }
+ }
+
+ /* init kernel params */
+ params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
+ memset(params, 0, sizeof(struct linux_params));
+ params->mount_root_rdonly = 0;
+ params->cl_magic = 0xA33F;
+ params->cl_offset = params->commandline - (uint8_t *)params;
+ params->alt_mem_k = (phys_ram_size / 1024) - 1024;
+ for(i = optind + 1; i < argc; i++) {
+ if (i != optind + 1)
+ pstrcat(params->commandline, sizeof(params->commandline), " ");
+ pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
+ }
+ params->loader_type = 0x01;
+ if (initrd_size > 0) {
+ params->initrd_start = INITRD_LOAD_ADDR;
+ params->initrd_size = initrd_size;
+ }
+ params->orig_video_lines = 25;
+ params->orig_video_cols = 80;
+
+ /* setup basic memory access */
+ env->cr[0] = 0x00000033;
+ cpu_x86_init_mmu(env);
+
+ memset(params->idt_table, 0, sizeof(params->idt_table));
+
+ params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
+ params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
+
+ env->idt.base = (void *)params->idt_table;
+ env->idt.limit = sizeof(params->idt_table) - 1;
+ env->gdt.base = (void *)params->gdt_table;
+ env->gdt.limit = sizeof(params->gdt_table) - 1;
+
+ cpu_x86_load_seg_cache(env, R_CS, KERNEL_CS, NULL, 0xffffffff, 0x00cf9a00);
+ cpu_x86_load_seg_cache(env, R_DS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
+ cpu_x86_load_seg_cache(env, R_ES, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
+ cpu_x86_load_seg_cache(env, R_SS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
+ cpu_x86_load_seg_cache(env, R_FS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
+ cpu_x86_load_seg_cache(env, R_GS, KERNEL_DS, NULL, 0xffffffff, 0x00cf9200);
+
+ env->eip = KERNEL_LOAD_ADDR;
+ env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
+ env->eflags = 0x2;
+
+ } else {
+ char buf[1024];
+
+ /* RAW PC boot */
+
+ /* BIOS load */
+ snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, BIOS_FILENAME);
+ ret = load_image(buf, phys_ram_base + 0x000f0000);
+ if (ret != 0x10000) {
+ fprintf(stderr, "vl: could not load PC bios '%s'\n", BIOS_FILENAME);
+ exit(1);
+ }
+
+ /* VGA BIOS load */
+ snprintf(buf, sizeof(buf), "%s/%s", interp_prefix, VGABIOS_FILENAME);
+ ret = load_image(buf, phys_ram_base + 0x000c0000);
+
+ /* setup basic memory access */
+ env->cr[0] = 0x60000010;
+ cpu_x86_init_mmu(env);
+
+ env->idt.limit = 0xffff;
+ env->gdt.limit = 0xffff;
+ env->ldt.limit = 0xffff;
+
+ /* not correct (CS base=0xffff0000) */
+ cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
+ cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
+ cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
+ cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
+ cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
+ cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
+
+ env->eip = 0xfff0;
+ env->regs[R_EDX] = 0x600; /* indicate P6 processor */
+
+ env->eflags = 0x2;
+
+ bochs_bios_init();
}
- params->orig_video_lines = 25;
- params->orig_video_cols = 80;
+ /* terminal init */
+ if (nodisp) {
+ dumb_display_init(ds);
+ } else {
+#ifdef CONFIG_SDL
+ sdl_display_init(ds);
+ /* SDL use the pthreads and they modify sigaction. We don't
+ want that. */
+#if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)
+#define sigaction __libc_sigaction
+#else
+#define sigaction __sigaction
+#endif
+#else
+ dumb_display_init(ds);
+#endif
+ }
/* init basic PC hardware */
- init_ioports();
- register_ioport_writeb(0x80, 1, ioport80_write);
-
- register_ioport_writeb(0x3d4, 2, vga_ioport_write);
+ register_ioport_write(0x80, 1, ioport80_write, 1);
+ vga_init(ds, phys_ram_base + phys_ram_size, phys_ram_size,
+ vga_ram_size);
cmos_init();
pic_init();
pit_init();
serial_init();
ne2000_init();
-
+ ide_init();
+ kbd_init();
+
/* setup cpu signal handlers for MMU / self modifying code handling */
sigfillset(&act.sa_mask);
act.sa_flags = SA_SIGINFO;
act.sa_sigaction = host_alarm_handler;
sigaction(SIGALRM, &act, NULL);
- /* init CPU state */
- env = cpu_init();
- global_env = env;
- cpu_single_env = env;
-
- /* setup basic memory access */
- env->cr[0] = 0x00000033;
- cpu_x86_init_mmu(env);
-
- memset(params->idt_table, 0, sizeof(params->idt_table));
-
- params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
- params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
-
- env->idt.base = (void *)params->idt_table;
- env->idt.limit = sizeof(params->idt_table) - 1;
- env->gdt.base = (void *)params->gdt_table;
- env->gdt.limit = sizeof(params->gdt_table) - 1;
-
- cpu_x86_load_seg(env, R_CS, KERNEL_CS);
- cpu_x86_load_seg(env, R_DS, KERNEL_DS);
- cpu_x86_load_seg(env, R_ES, KERNEL_DS);
- cpu_x86_load_seg(env, R_SS, KERNEL_DS);
- cpu_x86_load_seg(env, R_FS, KERNEL_DS);
- cpu_x86_load_seg(env, R_GS, KERNEL_DS);
-
- env->eip = KERNEL_LOAD_ADDR;
- env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
- env->eflags = 0x2;
-
itv.it_interval.tv_sec = 0;
itv.it_interval.tv_usec = 1000;
itv.it_value.tv_sec = 0;
/* we probe the tick duration of the kernel to inform the user if
the emulated kernel requested a too high timer frequency */
getitimer(ITIMER_REAL, &itv);
+ timer_ms = itv.it_interval.tv_usec / 1000;
pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
1000000;
projects / qemu.git / blobdiff