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UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
authorRay Ni <ray.ni@intel.com>
Wed, 12 Jun 2019 09:26:45 +0000 (17:26 +0800)
committerRay Ni <ray.ni@intel.com>
Wed, 10 Jul 2019 08:00:15 +0000 (16:00 +0800)
commit7365eb2c8cf1d7112330d09918c0c67e8d0b827a
tree470ff5cbaf3038ed534f98344c4791564e4ac5a7tree
parent7c5010c7f88b790f4524c4a5311819e3af5e2752commit | diff
UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946

The patch changes SMM environment to use 5 level paging when CPU
supports it.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c diff | blob | blame | history
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