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(parent: 8e73df6) | patch
RISC-V: Add debug support for accessing CSRs.
authorJim Wilson <jimw@sifive.com>
Fri, 15 Mar 2019 10:26:58 +0000 (03:26 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 19 Mar 2019 12:13:24 +0000 (05:13 -0700)
commit753e3fe207db08ce0ef0405e8452c3397c9b9308
tree38d16fb6f1b727dafe750f2e4f638d50f0803132tree
parent8e73df6aa3f2f0e5c26c03a94a88406616291815commit | diff
RISC-V: Add debug support for accessing CSRs.

Add a debugger field to CPURISCVState.  Add riscv_csrrw_debug function
to set it.  Disable mode checks when debugger field true.

Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230903.9215-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/cpu.h diff | blob | blame | history
target/riscv/csr.c diff | blob | blame | history
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