DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
- ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
- ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
- ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+ ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+ ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
--- /dev/null
+/** @file\r
+\r
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_V7_H__\r
+#define __ARM_V7_H__\r
+\r
+// Domain Access Control Register\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
+\r
+#define TRANSLATION_TABLE_SIZE (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
+\r
+// Translation table descriptor types\r
+#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
+\r
+// Section descriptor definitions\r
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
+\r
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
+\r
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
+\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
+\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
+\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
+\r
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
+#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \\r
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+#endif // __ARM_V7_H__\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
-\r
- All rights reserved. This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __CORTEX_A8_H__\r
-#define __CORTEX_A8_H__\r
-\r
-// Domain Access Control Register\r
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
-\r
-#define TRANSLATION_TABLE_SIZE (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
-\r
-// Translation table descriptor types\r
-#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))\r
-#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
-\r
-// Section descriptor definitions\r
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)\r
-#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)\r
-\r
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)\r
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)\r
-\r
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)\r
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)\r
-\r
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))\r
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))\r
-\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
-\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)\r
-\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
-\r
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
-#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
-#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \\r
- TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \\r
- TT_DESCRIPTOR_SECTION_NG_GLOBAL | \\r
- TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_AP_RW_RW | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
-\r
-#endif // __CORTEX_A8_H__\r
+++ /dev/null
-/** @file
-
- Copyright (c) 2008-2009, Apple Inc. All rights reserved.
-
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Chipset/Cortex-A8.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include "ArmCortexALib.h"
-
-VOID
-FillTranslationTable (
- IN UINT32 *TranslationTable,
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
- )
-{
- UINT32 *Entry;
- UINTN Sections;
- UINTN Index;
- UINT32 Attributes;
- UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
-
- switch (MemoryRegion->Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
- break;
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- default:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
- break;
- }
-
- Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
- Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
-
- for (Index = 0; Index < Sections; Index++) {
- *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
- }
-}
-
-VOID
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- )
-{
- VOID *TranslationTable;
-
- // Allocate pages for translation table.
- TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
- TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
-
- if (TranslationTableBase != NULL) {
- *TranslationTableBase = TranslationTable;
- }
-
- if (TranslationTableBase != NULL) {
- *TranslationTableSize = TRANSLATION_TABLE_SIZE;
- }
-
- ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
-
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
- ArmInvalidateTlb();
-
- ArmDisableDataCache();
- ArmDisableInstructionCache();
- ArmDisableMmu();
-
- // Make sure nothing sneaked into the cache
- ArmCleanInvalidateDataCache();
- ArmInvalidateInstructionCache();
-
- while (MemoryTable->Length != 0) {
- FillTranslationTable(TranslationTable, MemoryTable);
- MemoryTable++;
- }
-
- ArmSetTranslationTableBaseAddress(TranslationTable);
-
- ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
- DOMAIN_ACCESS_CONTROL_NONE(14) |
- DOMAIN_ACCESS_CONTROL_NONE(13) |
- DOMAIN_ACCESS_CONTROL_NONE(12) |
- DOMAIN_ACCESS_CONTROL_NONE(11) |
- DOMAIN_ACCESS_CONTROL_NONE(10) |
- DOMAIN_ACCESS_CONTROL_NONE( 9) |
- DOMAIN_ACCESS_CONTROL_NONE( 8) |
- DOMAIN_ACCESS_CONTROL_NONE( 7) |
- DOMAIN_ACCESS_CONTROL_NONE( 6) |
- DOMAIN_ACCESS_CONTROL_NONE( 5) |
- DOMAIN_ACCESS_CONTROL_NONE( 4) |
- DOMAIN_ACCESS_CONTROL_NONE( 3) |
- DOMAIN_ACCESS_CONTROL_NONE( 2) |
- DOMAIN_ACCESS_CONTROL_NONE( 1) |
- DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
- ArmEnableInstructionCache();
- ArmEnableDataCache();
- ArmEnableMmu();
-}
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- )
-{
- return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- )
-{
- return ARM_CACHE_ARCHITECTURE_SEPARATE;
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- )
-{
- return TRUE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- )
-{
- return 16 * 1024;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- )
-{
- return 4;
-}
-
-UINTN
-ArmDataCacheSets (
- VOID
- )
-{
- return 64;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
- VOID
- )
-{
- return 64;
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- )
-{
- return TRUE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- )
-{
- return 16 * 1024;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- )
-{
- return 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
- VOID
- )
-{
- return 64;
-}
-
-VOID
-ArmCortexADataCacheOperation (
- IN ARM_CORTEX_A_CACHE_OPERATION DataCacheOperation
- )
-{
- UINTN Set;
- UINTN SetCount;
- UINTN SetShift;
- UINTN Way;
- UINTN WayCount;
- UINTN WayShift;
- UINT32 SetWayFormat;
- UINTN SavedInterruptState;
-
- SetCount = ArmDataCacheSets();
- WayCount = ArmDataCacheAssociativity();
-
- // Cortex-A8 Manual, System Control Coprocessor chapter
- SetShift = 6;
- WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
-
- SavedInterruptState = ArmDisableInterrupts();
-
- for (Way = 0; Way < WayCount; Way++) {
- for (Set = 0; Set < SetCount; Set++) {
- // Build the format that the CP15 instruction can understand
- SetWayFormat = (Way << WayShift) | (Set << SetShift);
-
- // Pass it through
- (*DataCacheOperation)(SetWayFormat);
- }
- }
-
- ArmDrainWriteBuffer();
-
- if (SavedInterruptState) {
- ArmEnableInterrupts();
- }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
- VOID
- )
-{
- ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
- VOID
- )
-{
- ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
- VOID
- )
-{
- ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay);
-}
+++ /dev/null
-/** @file
-
- Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
-
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __ARMCORTEXALIB_H__
-#define __ARMCORTEXALIB_H__
-
-typedef VOID (*ARM_CORTEX_A_CACHE_OPERATION)(UINT32);
-
-VOID
-EFIAPI
-ArmDrainWriteBuffer (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINT32 SetWayFormat
- );
-
-#endif // __ARMCORTEXALIB_H__
-
+++ /dev/null
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
-#
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-.globl ASM_PFX(ArmInvalidateInstructionCache)
-.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
-.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
-.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
-.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
-.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
-.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
-.globl ASM_PFX(ArmDrainWriteBuffer)
-.globl ASM_PFX(ArmEnableMmu)
-.globl ASM_PFX(ArmDisableMmu)
-.globl ASM_PFX(ArmMmuEnabled)
-.globl ASM_PFX(ArmEnableDataCache)
-.globl ASM_PFX(ArmDisableDataCache)
-.globl ASM_PFX(ArmEnableInstructionCache)
-.globl ASM_PFX(ArmDisableInstructionCache)
-.globl ASM_PFX(ArmEnableExtendPTConfig)
-.globl ASM_PFX(ArmDisableExtendPTConfig)
-.globl ASM_PFX(ArmEnableBranchPrediction)
-.globl ASM_PFX(ArmDisableBranchPrediction)
-
-.set DC_ON, (0x1<<2)
-.set IC_ON, (0x1<<12)
-.set XP_ON, (0x1<<23)
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
- bx lr
-
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
- bx lr
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
- bx lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
- bx lr
-
-
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line
- bx lr
-
-
-ASM_PFX(ArmDrainWriteBuffer):
- mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
- bx lr
-
-
-ASM_PFX(ArmInvalidateInstructionCache):
- mov R0,#0
- mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
- bx LR
-
-ASM_PFX(ArmEnableMmu):
- mrc p15,0,R0,c1,c0,0
- orr R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- bx LR
-
-ASM_PFX(ArmMmuEnabled):
- mrc p15,0,R0,c1,c0,0
- and R0,R0,#1
- bx LR
-
-
-ASM_PFX(ArmDisableMmu):
- mov R0,#0
- mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
- mrc p15,0,R0,c1,c0,0
- bic R0,R0,#1
- mcr p15,0,R0,c1,c0,0 @Disable MMU
- mov R0,#0
- mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
- bx LR
-
-ASM_PFX(ArmEnableDataCache):
- ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmDisableDataCache):
- ldr R1,=DC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear C bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmEnableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- orr R0,R0,R1 @Set I bit
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmDisableInstructionCache):
- ldr R1,=IC_ON
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data
- bic R0,R0,R1 @Clear I bit.
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data
- bx LR
-
-ASM_PFX(ArmEnableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ASM_PFX(ArmDisableBranchPrediction):
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+++ /dev/null
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
-//
-// All rights reserved. This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
- EXPORT ArmInvalidateInstructionCache
- EXPORT ArmInvalidateDataCacheEntryByMVA
- EXPORT ArmCleanDataCacheEntryByMVA
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA
- EXPORT ArmInvalidateDataCacheEntryBySetWay
- EXPORT ArmCleanDataCacheEntryBySetWay
- EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
- EXPORT ArmDrainWriteBuffer
- EXPORT ArmEnableMmu
- EXPORT ArmDisableMmu
- EXPORT ArmMmuEnabled
- EXPORT ArmEnableDataCache
- EXPORT ArmDisableDataCache
- EXPORT ArmEnableInstructionCache
- EXPORT ArmDisableInstructionCache
- EXPORT ArmEnableBranchPrediction
- EXPORT ArmDisableBranchPrediction
-
-DC_ON EQU ( 0x1:SHL:2 )
-IC_ON EQU ( 0x1:SHL:12 )
-XP_ON EQU ( 0x1:SHL:23 )
-
-
- AREA ArmCacheLib, CODE, READONLY
- PRESERVE8
-
-
-ArmInvalidateDataCacheEntryByMVA
- MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- BX lr
-
-
-ArmCleanDataCacheEntryByMVA
- MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
- BX lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
- MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- BX lr
-
-
-ArmInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
- bx lr
-
-
-ArmCleanInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
- bx lr
-
-
-ArmCleanDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line
- bx lr
-
-
-ArmDrainWriteBuffer
- mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
- bx lr
-
-
-ArmInvalidateInstructionCache
- MOV R0,#0
- MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
- MOV R0,#0
- MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
- BX LR
-
-ArmEnableMmu
- mrc p15,0,R0,c1,c0,0
- orr R0,R0,#1
- mcr p15,0,R0,c1,c0,0
- bx LR
-
-ArmMmuEnabled
- mrc p15,0,R0,c1,c0,0
- and R0,R0,#1
- bx LR
-
-ArmDisableMmu
- mov R0,#0
- mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
- mrc p15,0,R0,c1,c0,0
- bic R0,R0,#1
- mcr p15,0,R0,c1,c0,0 ;Disable MMU
- mov R0,#0
- mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
- mov R0,#0
- mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
- bx LR
-
-ArmEnableDataCache
- LDR R1,=DC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- ORR R0,R0,R1 ;Set C bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmDisableDataCache
- LDR R1,=DC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- BIC R0,R0,R1 ;Clear C bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmEnableInstructionCache
- LDR R1,=IC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- ORR R0,R0,R1 ;Set I bit
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmDisableInstructionCache
- LDR R1,=IC_ON
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
- BIC R0,R0,R1 ;Clear I bit.
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
- BX LR
-
-ArmEnableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
-ArmDisableBranchPrediction
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00000800
- mcr p15, 0, r0, c1, c0, 0
- bx LR
-
- END
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc.\r
-#\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmCortexArmLib\r
- FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/ArmLibSupport.S | GCC\r
- ../Common/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
- \r
- ArmCortexASupport.S | GCC\r
- ArmCortexASupport.asm | RVCT\r
-\r
- ArmCortexALib.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- MemoryAllocationLib\r
- \r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc.\r
-#\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmCortexArmLibPrePi\r
- FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/ArmLibSupport.S | GCC\r
- ../Common/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
- \r
- ArmCortexASupport.S | GCC\r
- ArmCortexASupport.asm | RVCT\r
-\r
- ArmCortexALib.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- PrePiLib\r
- \r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
--- /dev/null
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/ArmV7.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include "ArmV7Lib.h"
+
+VOID
+FillTranslationTable (
+ IN UINT32 *TranslationTable,
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
+ )
+{
+ UINT32 *Entry;
+ UINTN Sections;
+ UINTN Index;
+ UINT32 Attributes;
+ UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
+
+ switch (MemoryRegion->Attributes) {
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ default:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+ break;
+ }
+
+ Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
+
+ for (Index = 0; Index < Sections; Index++) {
+ *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ )
+{
+ VOID *TranslationTable;
+
+ // Allocate pages for translation table.
+ TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+ TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableBase = TranslationTable;
+ }
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+ }
+
+ ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+ ArmInvalidateTlb();
+
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+
+ while (MemoryTable->Length != 0) {
+ FillTranslationTable(TranslationTable, MemoryTable);
+ MemoryTable++;
+ }
+
+ ArmSetTranslationTableBaseAddress(TranslationTable);
+
+ ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+ DOMAIN_ACCESS_CONTROL_NONE(14) |
+ DOMAIN_ACCESS_CONTROL_NONE(13) |
+ DOMAIN_ACCESS_CONTROL_NONE(12) |
+ DOMAIN_ACCESS_CONTROL_NONE(11) |
+ DOMAIN_ACCESS_CONTROL_NONE(10) |
+ DOMAIN_ACCESS_CONTROL_NONE( 9) |
+ DOMAIN_ACCESS_CONTROL_NONE( 8) |
+ DOMAIN_ACCESS_CONTROL_NONE( 7) |
+ DOMAIN_ACCESS_CONTROL_NONE( 6) |
+ DOMAIN_ACCESS_CONTROL_NONE( 5) |
+ DOMAIN_ACCESS_CONTROL_NONE( 4) |
+ DOMAIN_ACCESS_CONTROL_NONE( 3) |
+ DOMAIN_ACCESS_CONTROL_NONE( 2) |
+ DOMAIN_ACCESS_CONTROL_NONE( 1) |
+ DOMAIN_ACCESS_CONTROL_MANAGER(0));
+
+ ArmEnableInstructionCache();
+ ArmEnableDataCache();
+ ArmEnableMmu();
+}
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+ VOID
+ )
+{
+ return ARM_CACHE_TYPE_WRITE_BACK;
+}
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+ VOID
+ )
+{
+ return ARM_CACHE_ARCHITECTURE_SEPARATE;
+}
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheSize (
+ VOID
+ )
+{
+ return 16 * 1024;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+ VOID
+ )
+{
+ return 4;
+}
+
+UINTN
+ArmDataCacheSets (
+ VOID
+ )
+{
+ return 64;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ )
+{
+ return 64;
+}
+
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+ VOID
+ )
+{
+ return 16 * 1024;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+ VOID
+ )
+{
+ return 4;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ )
+{
+ return 64;
+}
+
+VOID
+ArmV7DataCacheOperation (
+ IN ARM_V7_CACHE_OPERATION DataCacheOperation
+ )
+{
+ UINTN Set;
+ UINTN SetCount;
+ UINTN SetShift;
+ UINTN Way;
+ UINTN WayCount;
+ UINTN WayShift;
+ UINT32 SetWayFormat;
+ UINTN SavedInterruptState;
+
+ SetCount = ArmDataCacheSets();
+ WayCount = ArmDataCacheAssociativity();
+
+ // ARMv7 Manual, System Control Coprocessor chapter
+ SetShift = 6;
+ WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
+
+ SavedInterruptState = ArmDisableInterrupts();
+
+ for (Way = 0; Way < WayCount; Way++) {
+ for (Set = 0; Set < SetCount; Set++) {
+ // Build the format that the CP15 instruction can understand
+ SetWayFormat = (Way << WayShift) | (Set << SetShift);
+
+ // Pass it through
+ (*DataCacheOperation)(SetWayFormat);
+ }
+ }
+
+ ArmDrainWriteBuffer();
+
+ if (SavedInterruptState) {
+ ArmEnableInterrupts();
+ }
+}
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+ VOID
+ )
+{
+ ArmV7DataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+ VOID
+ )
+{
+ ArmV7DataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+ VOID
+ )
+{
+ ArmV7DataCacheOperation(ArmCleanDataCacheEntryBySetWay);
+}
--- /dev/null
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_V7_LIB_H__
+#define __ARM_V7_LIB_H__
+
+typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
+
+VOID
+EFIAPI
+ArmDrainWriteBuffer (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+#endif // __ARM_V7_LIB_H__
+
--- /dev/null
+#/** @file\r
+# Semihosting serail port lib\r
+#\r
+# Copyright (c) 2008 - 2010, Apple Inc.\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmV7Lib\r
+ FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmLib\r
+\r
+[Sources.common]\r
+ ../Common/ArmLibSupport.S | GCC\r
+ ../Common/ArmLibSupport.asm | RVCT\r
+ ../Common/ArmLib.c\r
+ \r
+ ArmV7Support.S | GCC\r
+ ArmV7Support.asm | RVCT\r
+\r
+ ArmV7Lib.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ MemoryAllocationLib\r
+ \r
+[Protocols]\r
+ gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
--- /dev/null
+#/** @file\r
+# Semihosting serail port lib\r
+#\r
+# Copyright (c) 2008 - 2010, Apple Inc.\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmV7LibPrePi\r
+ FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmLib\r
+\r
+[Sources.common]\r
+ ../Common/ArmLibSupport.S | GCC\r
+ ../Common/ArmLibSupport.asm | RVCT\r
+ ../Common/ArmLib.c\r
+ \r
+ ArmV7Support.S | GCC\r
+ ArmV7Support.asm | RVCT\r
+\r
+ ArmV7Lib.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ PrePiLib\r
+ \r
+[Protocols]\r
+ gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
--- /dev/null
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmDrainWriteBuffer)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmMmuEnabled)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableExtendPTConfig)
+.globl ASM_PFX(ArmDisableExtendPTConfig)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line
+ bx lr
+
+
+ASM_PFX(ArmDrainWriteBuffer):
+ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
+ bx lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
+ bx LR
+
+ASM_PFX(ArmEnableMmu):
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ASM_PFX(ArmMmuEnabled):
+ mrc p15,0,R0,c1,c0,0
+ and R0,R0,#1
+ bx LR
+
+
+ASM_PFX(ArmDisableMmu):
+ mov R0,#0
+ mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0 @Disable MMU
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
+ bx LR
+
+ASM_PFX(ArmEnableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set I bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear I bit.
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--- /dev/null
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ArmInvalidateInstructionCache
+ EXPORT ArmInvalidateDataCacheEntryByMVA
+ EXPORT ArmCleanDataCacheEntryByMVA
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA
+ EXPORT ArmInvalidateDataCacheEntryBySetWay
+ EXPORT ArmCleanDataCacheEntryBySetWay
+ EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
+ EXPORT ArmDrainWriteBuffer
+ EXPORT ArmEnableMmu
+ EXPORT ArmDisableMmu
+ EXPORT ArmMmuEnabled
+ EXPORT ArmEnableDataCache
+ EXPORT ArmDisableDataCache
+ EXPORT ArmEnableInstructionCache
+ EXPORT ArmDisableInstructionCache
+ EXPORT ArmEnableBranchPrediction
+ EXPORT ArmDisableBranchPrediction
+
+DC_ON EQU ( 0x1:SHL:2 )
+IC_ON EQU ( 0x1:SHL:12 )
+XP_ON EQU ( 0x1:SHL:23 )
+
+
+ AREA ArmCacheLib, CODE, READONLY
+ PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ BX lr
+
+
+ArmCleanDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ BX lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
+ BX lr
+
+
+ArmInvalidateDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
+ bx lr
+
+
+ArmCleanInvalidateDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
+ bx lr
+
+
+ArmCleanDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line
+ bx lr
+
+
+ArmDrainWriteBuffer
+ mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
+ bx lr
+
+
+ArmInvalidateInstructionCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
+ BX LR
+
+ArmEnableMmu
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ArmMmuEnabled
+ mrc p15,0,R0,c1,c0,0
+ and R0,R0,#1
+ bx LR
+
+ArmDisableMmu
+ mov R0,#0
+ mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0 ;Disable MMU
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
+ bx LR
+
+ArmEnableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set I bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear I bit.
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ArmDisableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ END
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
!endif
- ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
[LibraryClasses.common.SEC]
- ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
- RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu 7-A --thumb
RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
################################################################################
[LibraryClasses.common]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
- ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv6
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
- RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8
- RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu 7-A
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu 7-A
################################################################################