Add the macros for interfacing with the QEMU feature added in QEMU commit
2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08).
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
//\r
#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
\r
//\r
#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
\r
+#define MCH_EXT_TSEG_MB 0x50\r
+#define MCH_EXT_TSEG_MB_QUERY 0xFFFF\r
+\r
#define MCH_GGC 0x52\r
#define MCH_GGC_IVD BIT1\r
\r
#define MCH_GGC 0x52\r
#define MCH_GGC_IVD BIT1\r
\r
#define MCH_ESMRAMC_SM_CACHE BIT5\r
#define MCH_ESMRAMC_SM_L1 BIT4\r
#define MCH_ESMRAMC_SM_L2 BIT3\r
#define MCH_ESMRAMC_SM_CACHE BIT5\r
#define MCH_ESMRAMC_SM_L1 BIT4\r
#define MCH_ESMRAMC_SM_L2 BIT3\r
+#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)\r
#define MCH_ESMRAMC_TSEG_8MB BIT2\r
#define MCH_ESMRAMC_TSEG_2MB BIT1\r
#define MCH_ESMRAMC_TSEG_1MB 0\r
#define MCH_ESMRAMC_TSEG_8MB BIT2\r
#define MCH_ESMRAMC_TSEG_2MB BIT1\r
#define MCH_ESMRAMC_TSEG_1MB 0\r