This commit is out of the scope for BZ-1409. The commit will remove the
call of RegisterForShadow() at the entry point of the driver. By doing so,
the driver is now possible to be executed without being re-loaded into
permanent memory.
Thus, this commit will update the NvmExpressPei driver to avoid updating
the content of a global variable.
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
/** @file\r
The DMA memory help function.\r
\r
/** @file\r
The DMA memory help function.\r
\r
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
#include "NvmExpressPei.h"\r
\r
\r
#include "NvmExpressPei.h"\r
\r
-EDKII_IOMMU_PPI *mIoMmu;\r
+/**\r
+ Get IOMMU PPI.\r
+\r
+ @return Pointer to IOMMU PPI.\r
+\r
+**/\r
+EDKII_IOMMU_PPI *\r
+GetIoMmu (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
+\r
+ IoMmu = NULL;\r
+ Status = PeiServicesLocatePpi (\r
+ &gEdkiiIoMmuPpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **) &IoMmu\r
+ );\r
+ if (!EFI_ERROR (Status) && (IoMmu != NULL)) {\r
+ return IoMmu;\r
+ }\r
+\r
+ return NULL;\r
+}\r
\r
/**\r
Provides the controller-specific addresses required to access system memory from a\r
\r
/**\r
Provides the controller-specific addresses required to access system memory from a\r
OUT VOID **Mapping\r
)\r
{\r
OUT VOID **Mapping\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Attribute;\r
-\r
- if (mIoMmu != NULL) {\r
- Status = mIoMmu->Map (\r
- mIoMmu,\r
- Operation,\r
- HostAddress,\r
- NumberOfBytes,\r
- DeviceAddress,\r
- Mapping\r
- );\r
+ EFI_STATUS Status;\r
+ UINT64 Attribute;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
+\r
+ IoMmu = GetIoMmu ();\r
+\r
+ if (IoMmu != NULL) {\r
+ Status = IoMmu->Map (\r
+ IoMmu,\r
+ Operation,\r
+ HostAddress,\r
+ NumberOfBytes,\r
+ DeviceAddress,\r
+ Mapping\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
ASSERT(FALSE);\r
return EFI_INVALID_PARAMETER;\r
}\r
ASSERT(FALSE);\r
return EFI_INVALID_PARAMETER;\r
}\r
- Status = mIoMmu->SetAttribute (\r
- mIoMmu,\r
- *Mapping,\r
- Attribute\r
- );\r
+ Status = IoMmu->SetAttribute (\r
+ IoMmu,\r
+ *Mapping,\r
+ Attribute\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
IN VOID *Mapping\r
)\r
{\r
IN VOID *Mapping\r
)\r
{\r
+ EFI_STATUS Status;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
+\r
+ IoMmu = GetIoMmu ();\r
- if (mIoMmu != NULL) {\r
- Status = mIoMmu->SetAttribute (mIoMmu, Mapping, 0);\r
- Status = mIoMmu->Unmap (mIoMmu, Mapping);\r
+ if (IoMmu != NULL) {\r
+ Status = IoMmu->SetAttribute (IoMmu, Mapping, 0);\r
+ Status = IoMmu->Unmap (IoMmu, Mapping);\r
} else {\r
Status = EFI_SUCCESS;\r
}\r
} else {\r
Status = EFI_SUCCESS;\r
}\r
EFI_STATUS Status;\r
UINTN NumberOfBytes;\r
EFI_PHYSICAL_ADDRESS HostPhyAddress;\r
EFI_STATUS Status;\r
UINTN NumberOfBytes;\r
EFI_PHYSICAL_ADDRESS HostPhyAddress;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
\r
*HostAddress = NULL;\r
*DeviceAddress = 0;\r
\r
\r
*HostAddress = NULL;\r
*DeviceAddress = 0;\r
\r
- if (mIoMmu != NULL) {\r
- Status = mIoMmu->AllocateBuffer (\r
- mIoMmu,\r
- EfiBootServicesData,\r
- Pages,\r
- HostAddress,\r
- 0\r
- );\r
+ IoMmu = GetIoMmu ();\r
+\r
+ if (IoMmu != NULL) {\r
+ Status = IoMmu->AllocateBuffer (\r
+ IoMmu,\r
+ EfiBootServicesData,\r
+ Pages,\r
+ HostAddress,\r
+ 0\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);\r
- Status = mIoMmu->Map (\r
- mIoMmu,\r
- EdkiiIoMmuOperationBusMasterCommonBuffer,\r
- *HostAddress,\r
- &NumberOfBytes,\r
- DeviceAddress,\r
- Mapping\r
- );\r
+ Status = IoMmu->Map (\r
+ IoMmu,\r
+ EdkiiIoMmuOperationBusMasterCommonBuffer,\r
+ *HostAddress,\r
+ &NumberOfBytes,\r
+ DeviceAddress,\r
+ Mapping\r
+ );\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
if (EFI_ERROR (Status)) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- Status = mIoMmu->SetAttribute (\r
- mIoMmu,\r
- *Mapping,\r
- EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE\r
- );\r
+ Status = IoMmu->SetAttribute (\r
+ IoMmu,\r
+ *Mapping,\r
+ EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
IN VOID *Mapping\r
)\r
{\r
IN VOID *Mapping\r
)\r
{\r
+ EFI_STATUS Status;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
- if (mIoMmu != NULL) {\r
- Status = mIoMmu->SetAttribute (mIoMmu, Mapping, 0);\r
- Status = mIoMmu->Unmap (mIoMmu, Mapping);\r
- Status = mIoMmu->FreeBuffer (mIoMmu, Pages, HostAddress);\r
+ IoMmu = GetIoMmu ();\r
+\r
+ if (IoMmu != NULL) {\r
+ Status = IoMmu->SetAttribute (IoMmu, Mapping, 0);\r
+ Status = IoMmu->Unmap (IoMmu, Mapping);\r
+ Status = IoMmu->FreeBuffer (IoMmu, Pages, HostAddress);\r
} else {\r
Status = EFI_SUCCESS;\r
}\r
return Status;\r
}\r
} else {\r
Status = EFI_SUCCESS;\r
}\r
return Status;\r
}\r
-\r
-/**\r
- Initialize IOMMU.\r
-**/\r
-VOID\r
-IoMmuInit (\r
- VOID\r
- )\r
-{\r
- PeiServicesLocatePpi (\r
- &gEdkiiIoMmuPpiGuid,\r
- 0,\r
- NULL,\r
- (VOID **)&mIoMmu\r
- );\r
-}\r
-\r
The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
which follows NVM Express specification at PEI phase.\r
\r
The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
which follows NVM Express specification at PEI phase.\r
\r
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;\r
EFI_PHYSICAL_ADDRESS DeviceAddress;\r
\r
PEI_NVME_CONTROLLER_PRIVATE_DATA *Private;\r
EFI_PHYSICAL_ADDRESS DeviceAddress;\r
\r
- //\r
- // Shadow this PEIM to run from memory\r
- //\r
- if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r
- return EFI_SUCCESS;\r
- }\r
-\r
//\r
// Locate the NVME host controller PPI\r
//\r
//\r
// Locate the NVME host controller PPI\r
//\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
Controller = 0;\r
MmioBase = 0;\r
while (TRUE) {\r
Controller = 0;\r
MmioBase = 0;\r
while (TRUE) {\r
The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
which follows NVM Express specification at PEI phase.\r
\r
The NvmExpressPei driver is used to manage non-volatile memory subsystem\r
which follows NVM Express specification at PEI phase.\r
\r
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
\r
\r
CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)\r
\r
\r
-/**\r
- Initialize IOMMU.\r
-**/\r
-VOID\r
-IoMmuInit (\r
- VOID\r
- );\r
+//\r
+// Internal functions\r
+//\r
\r
/**\r
Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
\r
/**\r
Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r