2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class.
3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311
6f19259b-4bc3-4df7-8a09-
765794883524
configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r
access to PCI Segment #0.\r
\r
configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r
access to PCI Segment #0.\r
\r
-Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
+ If the register specified by Address >= 0x100, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
accesses when PCI Segments other than Segment #0 must be accessed. \r
\r
access method. Modules will typically use the PCI Segment Library for its PCI configuration \r
accesses when PCI Segments other than Segment #0 must be accessed. \r
\r
-Copyright (c) 2006 - 2008, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
PCI CF8 Library functions that use I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
Layers on top of an I/O Library instance.\r
\r
PCI CF8 Library functions that use I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.\r
Layers on top of an I/O Library instance.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
\r
If Address > 0x0FFFFFFF, then ASSERT().\r
+ If the register specified by Address >= 0x100, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
return RETURN_SUCCESS;\r
}\r
\r
return RETURN_SUCCESS;\r
}\r
\r
All assertions for I/O operations are handled in MMIO functions in the IoLib\r
Library.\r
\r
All assertions for I/O operations are handled in MMIO functions in the IoLib\r
Library.\r
\r
- Copyright (c) 2006 - 2008, Intel Corporation<BR>\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_UNSUPPORTED;\r
}\r
\r
/** @file\r
PCI Library using PCI CFG2 PPI.\r
\r
/** @file\r
PCI Library using PCI CFG2 PPI.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+ Copyright (c) 2007 - 2009, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_UNSUPPORTED;\r
}\r
\r
/** @file\r
PCI Segment Library implementation using PCI CFG2 PPI.\r
\r
/** @file\r
PCI Segment Library implementation using PCI CFG2 PPI.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+ Copyright (c) 2007 - 2009, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
\r
/**\r
Assert the validity of a PCI Segment address.\r
\r
/**\r
Assert the validity of a PCI Segment address.\r
- A valid PCI Segment address should not contain 1's in bits 31:28\r
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
\r
@param A The address to validate.\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
\r
@param A The address to validate.\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
- ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
\r
/**\r
Translate PCI Lib address into format of PCI CFG2 PPI.\r
\r
/**\r
Translate PCI Lib address into format of PCI CFG2 PPI.\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_UNSUPPORTED;\r
}\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
/** @file\r
PCI Library using PCI Root Bridge I/O Protocol.\r
\r
/** @file\r
PCI Library using PCI Root Bridge I/O Protocol.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+ Copyright (c) 2007 - 2009, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_UNSUPPORTED;\r
}\r
\r
/** @file\r
PCI Segment Library implementation using PCI Root Bridge I/O Protocol.\r
\r
/** @file\r
PCI Segment Library implementation using PCI Root Bridge I/O Protocol.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+ Copyright (c) 2007 - 2009, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
Register a PCI device so PCI configuration registers may be accessed after \r
SetVirtualAddressMap().\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
\r
@param Address Address that encodes the PCI Bus, Device, Function and\r
Register.\r
IN UINTN Address\r
)\r
{\r
IN UINTN Address\r
)\r
{\r
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_UNSUPPORTED;\r
}\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
\r
- If Address > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in Address are set, then ASSERT().\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
\r
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
@param Value The value to write.\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
and 16-bit PCI configuration read cycles may be used at the beginning and the\r
end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
and the end of the range.\r
\r
- If StartAddress > 0x0FFFFFFF, then ASSERT().\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
/** @file\r
Include file of PciSegmentPciRootBridgeIo Library.\r
\r
/** @file\r
Include file of PciSegmentPciRootBridgeIo Library.\r
\r
- Copyright (c) 2007 - 2008, Intel Corporation All rights\r
+ Copyright (c) 2007 - 2009, Intel Corporation All rights\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
reserved. This program and the accompanying materials are\r
licensed and made available under the terms and conditions of\r
the BSD License which accompanies this distribution. The full\r
\r
/**\r
Assert the validity of a PCI Segment address.\r
\r
/**\r
Assert the validity of a PCI Segment address.\r
- A valid PCI address should not contain 1's in bits 31:28\r
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r
\r
@param A The address to validate.\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
\r
@param A The address to validate.\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
- ASSERT (((A) & (0xf0000000 | (M))) == 0)\r
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
\r
/**\r
Translate PCI Lib address into format of PCI Root Bridge I/O Protocol\r
\r
/**\r
Translate PCI Lib address into format of PCI Root Bridge I/O Protocol\r