+//\r
+// B/D/F/Type: 0/0/0/PCI\r
+//\r
+#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))\r
+\r
+#define MCH_GGC 0x52\r
+#define MCH_GGC_IVD BIT1\r
+\r
+#define MCH_SMRAM 0x9D\r
+#define MCH_SMRAM_D_LCK BIT4\r
+#define MCH_SMRAM_G_SMRAME BIT3\r
+\r
+#define MCH_ESMRAMC 0x9E\r
+#define MCH_ESMRAMC_H_SMRAME BIT7\r
+#define MCH_ESMRAMC_E_SMERR BIT6\r
+#define MCH_ESMRAMC_SM_CACHE BIT5\r
+#define MCH_ESMRAMC_SM_L1 BIT4\r
+#define MCH_ESMRAMC_SM_L2 BIT3\r
+#define MCH_ESMRAMC_TSEG_8MB BIT2\r
+#define MCH_ESMRAMC_TSEG_2MB BIT1\r
+#define MCH_ESMRAMC_TSEG_1MB 0\r
+#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)\r
+#define MCH_ESMRAMC_T_EN BIT0\r
+\r
+#define MCH_GBSM 0xA4\r
+#define MCH_GBSM_MB_SHIFT 20\r
+\r
+#define MCH_BGSM 0xA8\r
+#define MCH_BGSM_MB_SHIFT 20\r
+\r
+#define MCH_TSEGMB 0xAC\r
+#define MCH_TSEGMB_MB_SHIFT 20\r
+\r
+#define MCH_TOLUD 0xB0\r
+#define MCH_TOLUD_MB_SHIFT 4\r
+\r