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129ff94)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian, Feng <feng.tian@intel.com>
Reviewed-by: Li, Elvin <elvin.li@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15534
6f19259b-4bc3-4df7-8a09-
765794883524
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
+\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
@param[in] Address The memory address to test.\r
@param[in] MaskValue The mask value of memory.\r
@param[in] TestValue The test value of memory.\r
@param[in] Address The memory address to test.\r
@param[in] MaskValue The mask value of memory.\r
@param[in] TestValue The test value of memory.\r
- @param[in, out] RetryTimes The retry times value for waitting memory set. If 0, then just try once.\r
+ @param[in, out] Task Optional. Pointer to the ATA_NONBLOCK_TASK used by\r
+ non-blocking mode. If NULL, then just try once.\r
\r
@retval EFI_NOTREADY The memory is not set.\r
@retval EFI_TIMEOUT The memory setting retry times out.\r
\r
@retval EFI_NOTREADY The memory is not set.\r
@retval EFI_TIMEOUT The memory setting retry times out.\r
IN UINTN Address,\r
IN UINT32 MaskValue,\r
IN UINT32 TestValue,\r
IN UINTN Address,\r
IN UINT32 MaskValue,\r
IN UINT32 TestValue,\r
- IN OUT UINTN *RetryTimes OPTIONAL\r
+ IN OUT ATA_NONBLOCK_TASK *Task\r
)\r
{\r
UINT32 Value;\r
\r
)\r
{\r
UINT32 Value;\r
\r
- if (RetryTimes != NULL) {\r
- (*RetryTimes)--;\r
+ if (Task != NULL) {\r
+ Task->RetryTimes--;\r
}\r
\r
Value = *(volatile UINT32 *) Address;\r
}\r
\r
Value = *(volatile UINT32 *) Address;\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
- if ((RetryTimes != NULL) && (*RetryTimes == 0)) {\r
+ if ((Task != NULL) && !Task->InfiniteWait && (Task->RetryTimes == 0)) {\r
return EFI_TIMEOUT;\r
} else {\r
return EFI_NOT_READY;\r
return EFI_TIMEOUT;\r
} else {\r
return EFI_NOT_READY;\r
VOID *Map;\r
UINTN MapLength;\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
VOID *Map;\r
UINTN MapLength;\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
EFI_AHCI_COMMAND_FIS CFis;\r
EFI_AHCI_COMMAND_LIST CmdList;\r
UINT32 PortTfd;\r
UINT32 PrdCount;\r
EFI_AHCI_COMMAND_FIS CFis;\r
EFI_AHCI_COMMAND_LIST CmdList;\r
UINT32 PortTfd;\r
UINT32 PrdCount;\r
+ BOOLEAN InfiniteWait;\r
+\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
// Wait device sends the PIO setup fis before data transfer\r
//\r
Status = EFI_TIMEOUT;\r
// Wait device sends the PIO setup fis before data transfer\r
//\r
Status = EFI_TIMEOUT;\r
- Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
do {\r
Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;\r
\r
do {\r
Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;\r
\r
- Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, 0);\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, NULL);\r
if (!EFI_ERROR (Status)) {\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
if (!EFI_ERROR (Status)) {\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
}\r
\r
Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
}\r
\r
Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
- Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, 0);\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);\r
if (!EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
break;\r
if (!EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
break;\r
MicroSecondDelay(100);\r
\r
Delay--;\r
MicroSecondDelay(100);\r
\r
Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
} else {\r
//\r
// Wait for D2H Fis is received\r
} else {\r
//\r
// Wait for D2H Fis is received\r
//\r
if (Task != NULL) {\r
Task->IsStart = TRUE;\r
//\r
if (Task != NULL) {\r
Task->IsStart = TRUE;\r
- Task->RetryTimes = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
}\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
}\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
Offset,\r
EFI_AHCI_FIS_TYPE_MASK,\r
EFI_AHCI_FIS_REGISTER_D2H,\r
Offset,\r
EFI_AHCI_FIS_TYPE_MASK,\r
EFI_AHCI_FIS_REGISTER_D2H,\r
- (UINTN *) (&Task->RetryTimes)\r
);\r
} else {\r
Status = AhciWaitMemSet (\r
);\r
} else {\r
Status = AhciWaitMemSet (\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT32 Value;\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);\r
\r
UINT32 Value;\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);\r
\r
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
\r
do {\r
Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
\r
do {\r
Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);\r
Task->Packet = Packet;\r
Task->Event = Event;\r
Task->IsStart = FALSE;\r
Task->Packet = Packet;\r
Task->Event = Event;\r
Task->IsStart = FALSE;\r
- Task->RetryTimes = 0;\r
+ Task->RetryTimes = DivU64x32(Packet->Timeout, 1000) + 1;\r
+ if (Packet->Timeout == 0) {\r
+ Task->InfiniteWait = TRUE;\r
+ } else {\r
+ Task->InfiniteWait = FALSE;\r
+ }\r
\r
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
InsertTailList (&Instance->NonBlockingTaskList, &Task->Link);\r
\r
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
InsertTailList (&Instance->NonBlockingTaskList, &Task->Link);\r
BOOLEAN IsStart;\r
EFI_EVENT Event;\r
UINT64 RetryTimes;\r
BOOLEAN IsStart;\r
EFI_EVENT Event;\r
UINT64 RetryTimes;\r
- VOID *Map; // Pointer to map.\r
- VOID *TableMap;// Pointer to PRD table map.\r
+ BOOLEAN InfiniteWait;\r
+ VOID *Map; // Pointer to map.\r
+ VOID *TableMap; // Pointer to PRD table map.\r
EFI_ATA_DMA_PRD *MapBaseAddress; // Pointer to range Base address for Map.\r
EFI_ATA_DMA_PRD *MapBaseAddress; // Pointer to range Base address for Map.\r
- UINTN PageCount; // The page numbers used by PCIO freebuffer.\r
+ UINTN PageCount; // The page numbers used by PCIO freebuffer.\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT8 StatusRegister;\r
UINT8 ErrorRegister;\r
UINT8 StatusRegister;\r
UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
//\r
// Read Status Register will clear interrupt\r
do {\r
//\r
// Read Status Register will clear interrupt\r
MicroSecondDelay (100);\r
\r
Delay--;\r
MicroSecondDelay (100);\r
\r
Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT8 AltRegister;\r
UINT8 ErrorRegister;\r
UINT8 AltRegister;\r
UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
MicroSecondDelay (100);\r
\r
Delay--;\r
MicroSecondDelay (100);\r
\r
Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT8 StatusRegister;\r
UINT8 ErrorRegister;\r
UINT8 StatusRegister;\r
UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
//\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
//\r
MicroSecondDelay (100);\r
\r
Delay--;\r
MicroSecondDelay (100);\r
\r
Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT8 AltRegister;\r
UINT8 ErrorRegister;\r
UINT8 AltRegister;\r
UINT8 ErrorRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
//\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
//\r
MicroSecondDelay (100);\r
\r
Delay--;\r
MicroSecondDelay (100);\r
\r
Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
IN UINT64 Timeout\r
)\r
{\r
IN UINT64 Timeout\r
)\r
{\r
UINT8 AltStatusRegister;\r
UINT8 AltStatusRegister;\r
+ BOOLEAN InfiniteWait;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+\r
+ Delay = DivU64x32(Timeout, 1000) + 1;\r
do {\r
AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
do {\r
AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
+ } while (InfiniteWait || (Delay > 0));\r
\r
return EFI_TIMEOUT;\r
}\r
\r
return EFI_TIMEOUT;\r
}\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
+ @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The memory is not set.\r
@retval EFI_TIMEOUT The memory setting is time out.\r
\r
@retval EFI_DEVICE_ERROR The memory is not set.\r
@retval EFI_TIMEOUT The memory setting is time out.\r
**/\r
EFI_STATUS\r
AtaUdmStatusWait (\r
**/\r
EFI_STATUS\r
AtaUdmStatusWait (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_IDE_REGISTERS *IdeRegisters\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN EFI_IDE_REGISTERS *IdeRegisters,\r
+ IN UINT64 Timeout\r
)\r
{\r
UINT8 RegisterValue;\r
EFI_STATUS Status;\r
UINT16 IoPortForBmis;\r
)\r
{\r
UINT8 RegisterValue;\r
EFI_STATUS Status;\r
UINT16 IoPortForBmis;\r
+ UINT64 Delay;\r
+ BOOLEAN InfiniteWait;\r
+\r
+ if (Timeout == 0) {\r
+ InfiniteWait = TRUE;\r
+ } else {\r
+ InfiniteWait = FALSE;\r
+ }\r
+ Delay = DivU64x32 (Timeout, 1000) + 1;\r
Status = CheckStatusRegister (PciIo, IdeRegisters);\r
if (EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
Status = CheckStatusRegister (PciIo, IdeRegisters);\r
if (EFI_ERROR (Status)) {\r
Status = EFI_DEVICE_ERROR;\r
- // Stall for 1 milliseconds.\r
+ // Stall for 100 microseconds.\r
- MicroSecondDelay (1000);\r
- Timeout--;\r
- }\r
+ MicroSecondDelay (100);\r
+ Delay--;\r
+ } while (InfiniteWait || (Delay > 0));\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
- if (Task->RetryTimes == 0) {\r
+ if (!Task->InfiniteWait && (Task->RetryTimes == 0)) {\r
return EFI_TIMEOUT;\r
} else {\r
//\r
return EFI_TIMEOUT;\r
} else {\r
//\r
IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
\r
if (Task != NULL) {\r
IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);\r
\r
if (Task != NULL) {\r
- //\r
- // Max transfer number of sectors for one command is 65536(32Mbyte),\r
- // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).\r
- // So set the variable Count to 2000, for about 2 second Timeout time.\r
- //\r
- Task->RetryTimes = 2000;\r
Task->Map = BufferMap;\r
Task->TableMap = PrdTableMap;\r
Task->MapBaseAddress = PrdBaseAddr;\r
Task->Map = BufferMap;\r
Task->TableMap = PrdTableMap;\r
Task->MapBaseAddress = PrdBaseAddr;\r
\r
//\r
// Check the INTERRUPT and ERROR bit of BMIS\r
\r
//\r
// Check the INTERRUPT and ERROR bit of BMIS\r
- // Max transfer number of sectors for one command is 65536(32Mbyte),\r
- // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).\r
- // So set the variable Count to 2000, for about 2 second Timeout time.\r
//\r
if (Task != NULL) {\r
Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);\r
} else {\r
//\r
if (Task != NULL) {\r
Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);\r
} else {\r
- Status = AtaUdmStatusWait (PciIo, IdeRegisters);\r
+ Status = AtaUdmStatusWait (PciIo, IdeRegisters, Timeout);\r