According to SMBIOS 3.4, section 7.5.3.3 ARM64-class CPUs, if
SMCCC_ARCH_SOC_ID is supported, the first DWORD is the JEP-106 code and
the second DWORD is the SoC revision value. But in the current
implementation, they are set in reverse. This patch is to correct it.
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Rebecca Cran <rebecca@nuviainc.com>
Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
Functions for processor information common to ARM and AARCH64.\r
\r
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
Functions for processor information common to ARM and AARCH64.\r
\r
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>\r
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
if (HasSmcArm64SocId ()) {\r
SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);\r
\r
if (HasSmcArm64SocId ()) {\r
SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);\r
- ProcessorId = ((UINT64)Jep106Code << 32) | SocRevision;\r
+ ProcessorId = ((UINT64)SocRevision << 32) | Jep106Code;\r
} else {\r
ProcessorId = ArmReadMidr ();\r
}\r
} else {\r
ProcessorId = ArmReadMidr ();\r
}\r