+\r
+/// Defines the structure of the CSSELR (Cache Size Selection) register\r
+typedef union {\r
+ struct {\r
+ UINT32 InD :1; ///< Instruction not Data bit\r
+ UINT32 Level :3; ///< Cache level (zero based)\r
+ UINT32 TnD :1; ///< Allocation not Data bit\r
+ UINT32 Reserved :27; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
+} CSSELR_DATA;\r
+\r
+/// The cache type values for the InD field of the CSSELR register\r
+typedef enum\r
+{\r
+ /// Select the data or unified cache\r
+ CsselrCacheTypeDataOrUnified = 0,\r
+ /// Select the instruction cache\r
+ CsselrCacheTypeInstruction,\r
+ CsselrCacheTypeMax\r
+} CSSELR_CACHE_TYPE;\r
+\r
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
+typedef union {\r
+ struct {\r
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity :10; ///< Associativity - 1\r
+ UINT64 NumSets :15; ///< Number of sets in the cache -1\r
+ UINT64 Unknown :4; ///< Reserved, UNKNOWN\r
+ UINT64 Reserved :32; ///< Reserved, RES0\r
+ } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
+ struct {\r
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)\r
+ UINT64 Associativity :21; ///< Associativity - 1\r
+ UINT64 Reserved1 :8; ///< Reserved, RES0\r
+ UINT64 NumSets :24; ///< Number of sets in the cache -1\r
+ UINT64 Reserved2 :8; ///< Reserved, RES0\r
+ } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
+ struct {\r
+ UINT64 LineSize : 3;\r
+ UINT64 Associativity : 21;\r
+ UINT64 Reserved : 8;\r
+ UINT64 Unallocated : 32;\r
+ } BitsCcidxAA32;\r
+ UINT64 Data; ///< The entire 64-bit value\r
+} CCSIDR_DATA;\r
+\r
+/// Defines the structure of the AARCH32 CCSIDR2 register.\r
+typedef union {\r
+ struct {\r
+ UINT32 NumSets :24; ///< Number of sets in the cache - 1\r
+ UINT32 Reserved :8; ///< Reserved, RES0\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
+} CCSIDR2_DATA;\r
+\r
+/** Defines the structure of the CLIDR (Cache Level ID) register.\r
+ *\r
+ * The lower 32 bits are the same for both AARCH32 and AARCH64\r
+ * so we can use the same structure for both.\r
+**/\r
+typedef union {\r
+ struct {\r
+ UINT32 Ctype1 : 3; ///< Level 1 cache type\r
+ UINT32 Ctype2 : 3; ///< Level 2 cache type\r
+ UINT32 Ctype3 : 3; ///< Level 3 cache type\r
+ UINT32 Ctype4 : 3; ///< Level 4 cache type\r
+ UINT32 Ctype5 : 3; ///< Level 5 cache type\r
+ UINT32 Ctype6 : 3; ///< Level 6 cache type\r
+ UINT32 Ctype7 : 3; ///< Level 7 cache type\r
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable\r
+ UINT32 LoC : 3; ///< Level of Coherency\r
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor\r
+ UINT32 Icb : 3; ///< Inner Cache Boundary\r
+ } Bits; ///< Bitfield definition of the register\r
+ UINT32 Data; ///< The entire 32-bit value\r
+} CLIDR_DATA;\r
+\r
+/// The cache types reported in the CLIDR register.\r
+typedef enum {\r
+ /// No cache is present\r
+ ClidrCacheTypeNone = 0,\r
+ /// There is only an instruction cache\r
+ ClidrCacheTypeInstructionOnly,\r
+ /// There is only a data cache\r
+ ClidrCacheTypeDataOnly,\r
+ /// There are separate data and instruction caches\r
+ ClidrCacheTypeSeparate,\r
+ /// There is a unified cache\r
+ ClidrCacheTypeUnified,\r
+ ClidrCacheTypeMax\r
+} CLIDR_CACHE_TYPE;\r
+\r
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
+\r