+#\r
+# Copyright (c) 2014, ARM Limited. All rights reserved.\r
+#\r
+# This program and the accompanying materials are licensed and made available\r
+# under the terms and conditions of the BSD License which accompanies this\r
+# distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/ArmLib.h>\r
+\r
+// For the moment we assume this will run in SVC mode on ARMv7\r
+\r
+.text\r
+.align 2\r
+\r
+GCC_ASM_EXPORT(ArmGicGetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicSetControlSystemRegisterEnable)\r
+GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface)\r
+GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt)\r
+GCC_ASM_EXPORT(ArmGicV3SetPriorityMask)\r
+GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer)\r
+\r
+//UINT32\r
+//EFIAPI\r
+//ArmGicGetControlSystemRegisterEnable (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGicGetControlSystemRegisterEnable):\r
+ mrc p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+ bx lr\r
+\r
+//VOID\r
+//EFIAPI\r
+//ArmGicSetControlSystemRegisterEnable (\r
+// IN UINT32 ControlSystemRegisterEnable\r
+// );\r
+ASM_PFX(ArmGicSetControlSystemRegisterEnable):\r
+ mcr p15, 0, r0, c12, c12, 5 // ICC_SRE\r
+ isb\r
+ bx lr\r
+\r
+//VOID\r
+//ArmGicV3EnableInterruptInterface (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGicV3EnableInterruptInterface):\r
+ mov r0, #1\r
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+ bx lr\r
+\r
+//VOID\r
+//ArmGicV3DisableInterruptInterface (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGicV3DisableInterruptInterface):\r
+ mov r0, #0\r
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1\r
+ bx lr\r
+\r
+//VOID\r
+//ArmGicV3EndOfInterrupt (\r
+// IN UINTN InterruptId\r
+// );\r
+ASM_PFX(ArmGicV3EndOfInterrupt):\r
+ mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1\r
+ bx lr\r
+\r
+//UINTN\r
+//ArmGicV3AcknowledgeInterrupt (\r
+// VOID\r
+// );\r
+ASM_PFX(ArmGicV3AcknowledgeInterrupt):\r
+ mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1\r
+ bx lr\r
+\r
+//VOID\r
+//ArmGicV3SetPriorityMask (\r
+// IN UINTN Priority\r
+// );\r
+ASM_PFX(ArmGicV3SetPriorityMask):\r
+ mcr p15, 0, r0, c4, c6, 0 //ICC_PMR\r
+ bx lr\r
+\r
+//VOID\r
+//ArmGicV3SetBinaryPointer (\r
+// IN UINTN BinaryPoint\r
+// );\r
+ASM_PFX(ArmGicV3SetBinaryPointer):\r
+ mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1\r
+ bx lr\r