From the AArch64 Procedure Call Standard (ARM IHI 0055B):
5.2.2.1 Universal stack constraints
At all times the following basic constraints must hold:
- SP mod 16 = 0. The stack must be quad-word aligned.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327
6f19259b-4bc3-4df7-8a09-
765794883524
GCC_ASM_EXPORT(ArmCallHvc)\r
\r
ASM_PFX(ArmCallHvc):\r
GCC_ASM_EXPORT(ArmCallHvc)\r
\r
ASM_PFX(ArmCallHvc):\r
- // Push x0 on the stack\r
- str x0, [sp, #-8]!\r
+ // Push x0 on the stack - The stack must always be quad-word aligned\r
+ str x0, [sp, #-16]!\r
\r
// Load the HVC arguments values into the appropriate registers\r
ldp x6, x7, [x0, #48]\r
\r
// Load the HVC arguments values into the appropriate registers\r
ldp x6, x7, [x0, #48]\r
hvc #0\r
\r
// Pop the ARM_HVC_ARGS structure address from the stack into x9\r
hvc #0\r
\r
// Pop the ARM_HVC_ARGS structure address from the stack into x9\r
- // Store the HVC returned values into the appropriate registers\r
+ // Store the HVC returned values into the ARM_HVC_ARGS structure.\r
// A HVC call can return up to 4 values\r
stp x2, x3, [x9, #16]\r
stp x0, x1, [x9, #0]\r
// A HVC call can return up to 4 values\r
stp x2, x3, [x9, #16]\r
stp x0, x1, [x9, #0]\r
\r
ASM_PFX(AArch64AllDataCachesOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
\r
ASM_PFX(AArch64AllDataCachesOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
- str x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+ str x30, [sp, #-16]!\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r
\r
ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
\r
ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
- str x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+ str x30, [sp, #-16]!\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)\r
GCC_ASM_EXPORT(ArmCallSmc)\r
\r
ASM_PFX(ArmCallSmc):\r
GCC_ASM_EXPORT(ArmCallSmc)\r
\r
ASM_PFX(ArmCallSmc):\r
- // Push x0 on the stack\r
- str x0, [sp, #-8]!\r
+ // Push x0 on the stack - The stack must always be quad-word aligned\r
+ str x0, [sp, #-16]!\r
\r
// Load the SMC arguments values into the appropriate registers\r
ldp x6, x7, [x0, #48]\r
\r
// Load the SMC arguments values into the appropriate registers\r
ldp x6, x7, [x0, #48]\r
smc #0\r
\r
// Pop the ARM_SMC_ARGS structure address from the stack into x9\r
smc #0\r
\r
// Pop the ARM_SMC_ARGS structure address from the stack into x9\r
- // Store the SMC returned values into the appropriate registers\r
+ // Store the SMC returned values into the ARM_SMC_ARGS structure.\r
// A SMC call can return up to 4 values - we do not need to store back x4-x7.\r
stp x2, x3, [x9, #16]\r
stp x0, x1, [x9, #0]\r
// A SMC call can return up to 4 values - we do not need to store back x4-x7.\r
stp x2, x3, [x9, #16]\r
stp x0, x1, [x9, #0]\r