gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf\r
\r
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
\r
ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
- ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
- ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
\r
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicGetMaxNumInterrupts (\r
+ IN INTN GicDistributorBase\r
+ )\r
+{\r
+ return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicSendSgiTo (\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList,\r
+ IN INTN SgiId\r
+ )\r
+{\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
+}\r
+\r
+RETURN_STATUS\r
+EFIAPI\r
+ArmGicAcknowledgeInterrupt (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN GicInterruptInterfaceBase,\r
+ OUT UINTN *CoreId,\r
+ OUT UINTN *InterruptId\r
+ )\r
+{\r
+ UINT32 Interrupt;\r
+\r
+ // Read the Interrupt Acknowledge Register\r
+ Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+\r
+ // Check if it is a valid interrupt ID\r
+ if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
+ // Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Interrupt);\r
+\r
+ if (CoreId) {\r
+ *CoreId = (Interrupt >> 10) & 0x7;\r
+ }\r
+ if (InterruptId) {\r
+ *InterruptId = Interrupt & 0x3FF;\r
+ }\r
+ return RETURN_SUCCESS;\r
+ } else {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
+Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r
+\r
+This program and the accompanying materials \r
+are licensed and made available under the terms and conditions of the BSD License \r
+which accompanies this distribution. The full text of the license may be found at \r
+http://opensource.org/licenses/bsd-license.php \r
+ \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+Module Name:\r
+\r
+ Gic.c\r
+\r
+Abstract:\r
+\r
+ Driver implementing the GIC interrupt controller protocol\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/HardwareInterrupt.h>\r
+\r
+#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
+\r
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
+\r
+//\r
+// Notifications\r
+//\r
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
+\r
+// Maximum Number of Interrupts\r
+UINTN mGicNumInterrupts = 0;\r
+\r
+HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;\r
+\r
+/**\r
+ Register Handler for the specified interrupt source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+ @param Handler Callback for interrupt. NULL to unregister\r
+\r
+ @retval EFI_SUCCESS Source was updated to support Handler.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+RegisterInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN HARDWARE_INTERRUPT_HANDLER Handler\r
+ )\r
+{\r
+ if (Source > mGicNumInterrupts) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
+ return EFI_ALREADY_STARTED;\r
+ }\r
+\r
+ gRegisteredInterruptHandlers[Source] = Handler;\r
+\r
+ // If the interrupt handler is unregistered then disable the interrupt\r
+ if (NULL == Handler){\r
+ return This->DisableInterruptSource (This, Source);\r
+ } else {\r
+ return This->EnableInterruptSource (This, Source);\r
+ }\r
+}\r
+\r
+/**\r
+ Enable interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt enabled.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EnableInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > mGicNumInterrupts) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // Calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+\r
+ // Write set-enable register\r
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Disable interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt disabled.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DisableInterruptSource (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > mGicNumInterrupts) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // Calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+\r
+ // Write set-enable register\r
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Return current state of interrupt source Source.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.\r
+\r
+ @retval EFI_SUCCESS InterruptState is valid\r
+ @retval EFI_DEVICE_ERROR InterruptState is not valid\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetInterruptSourceState (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source,\r
+ IN BOOLEAN *InterruptState\r
+ )\r
+{\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ \r
+ if (Source > mGicNumInterrupts) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ \r
+ // calculate enable register offset and bit position\r
+ RegOffset = Source / 32;\r
+ RegShift = Source % 32;\r
+ \r
+ if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r
+ *InterruptState = FALSE;\r
+ } else {\r
+ *InterruptState = TRUE;\r
+ }\r
+ \r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Signal to the hardware that the End Of Intrrupt state \r
+ has been reached.\r
+\r
+ @param This Instance pointer for this protocol\r
+ @param Source Hardware source of the interrupt\r
+\r
+ @retval EFI_SUCCESS Source interrupt EOI'ed.\r
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfInterrupt (\r
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
+ IN HARDWARE_INTERRUPT_SOURCE Source\r
+ )\r
+{\r
+ if (Source > mGicNumInterrupts) {\r
+ ASSERT(FALSE);\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
+\r
+ @param InterruptType Defines the type of interrupt or exception that\r
+ occurred on the processor.This parameter is processor architecture specific.\r
+ @param SystemContext A pointer to the processor context when\r
+ the interrupt occurred on the processor.\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+IrqInterruptHandler (\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
+ )\r
+{\r
+ UINT32 GicInterrupt;\r
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
+\r
+ GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r
+\r
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
+ if (GicInterrupt >= mGicNumInterrupts) {\r
+ // The special interrupt do not need to be acknowledge\r
+ return;\r
+ }\r
+ \r
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
+ if (InterruptHandler != NULL) {\r
+ // Call the registered interrupt handler.\r
+ InterruptHandler (GicInterrupt, SystemContext);\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
+ }\r
+\r
+ EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
+}\r
+\r
+//\r
+// Making this global saves a few bytes in image size\r
+//\r
+EFI_HANDLE gHardwareInterruptHandle = NULL;\r
+\r
+//\r
+// The protocol instance produced by this driver\r
+//\r
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
+ RegisterInterruptSource,\r
+ EnableInterruptSource,\r
+ DisableInterruptSource,\r
+ GetInterruptSourceState,\r
+ EndOfInterrupt\r
+};\r
+\r
+/**\r
+ Shutdown our hardware\r
+ \r
+ DXE Core will disable interrupts and turn off the timer and disable interrupts\r
+ after all the event handlers have run.\r
+\r
+ @param[in] Event The Event that is being processed\r
+ @param[in] Context Event Context\r
+**/\r
+VOID\r
+EFIAPI\r
+ExitBootServicesEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ UINTN Index;\r
+ \r
+ // Acknowledge all pending interrupts\r
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
+ }\r
+\r
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
+ EndOfInterrupt (&gHardwareInterruptProtocol, Index);\r
+ }\r
+\r
+ // Disable Gic Interface\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r
+\r
+ // Disable Gic Distributor\r
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r
+}\r
+\r
+/**\r
+ Initialize the state information for the CPU Architectural Protocol\r
+\r
+ @param ImageHandle of the loaded driver\r
+ @param SystemTable Pointer to the System Table\r
+\r
+ @retval EFI_SUCCESS Protocol registered\r
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
+ @retval EFI_DEVICE_ERROR Hardware problems\r
+\r
+**/\r
+EFI_STATUS\r
+InterruptDxeInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINT32 RegOffset;\r
+ UINTN RegShift;\r
+ EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+ UINT32 CpuTarget;\r
+ \r
+ // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
+\r
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));\r
+\r
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
+ \r
+ // Set Priority \r
+ RegOffset = Index / 4;\r
+ RegShift = (Index % 4) * 8;\r
+ MmioAndThenOr32 (\r
+ PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),\r
+ ~(0xff << RegShift), \r
+ ARM_GIC_DEFAULT_PRIORITY << RegShift\r
+ );\r
+ }\r
+\r
+ //\r
+ // Targets the interrupts to the Primary Cpu\r
+ //\r
+\r
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
+ // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
+ // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
+ // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
+ //\r
+ // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
+ // first SGIs)\r
+ CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
+\r
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
+ // is 0 when we run on a uniprocessor platform.\r
+ if (CpuTarget != 0) {\r
+ // The 8 first Interrupt Processor Targets Registers are read-only\r
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
+ MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+ }\r
+ }\r
+\r
+ // Set binary point reg to 0x7 (no preemption)\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);\r
+\r
+ // Set priority mask reg to 0xff to allow all priorities through\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
+ \r
+ // Enable gic cpu interface\r
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r
+\r
+ // Enable gic distributor\r
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r
+ \r
+ // Initialize the array for the Interrupt Handlers\r
+ gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
+ \r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &gHardwareInterruptHandle,\r
+ &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ \r
+ //\r
+ // Get the CPU protocol that this driver requires.\r
+ //\r
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ //\r
+ // Unregister the default exception handler.\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ //\r
+ // Register to receive interrupts\r
+ //\r
+ Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ // Register for an ExitBootServicesEvent\r
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+#/** @file\r
+# \r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmGicDxe\r
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 \r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InterruptDxeInitialize\r
+\r
+\r
+[Sources.common]\r
+ ArmGic.c\r
+ ArmGicDxe.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ UefiLib\r
+ UefiBootServicesTableLib\r
+ DebugLib\r
+ PrintLib\r
+ MemoryAllocationLib\r
+ UefiDriverEntryPoint\r
+ IoLib\r
+\r
+[Protocols]\r
+ gHardwareInterruptProtocolGuid\r
+ gEfiCpuArchProtocolGuid\r
+ \r
+[FixedPcd.common]\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+ \r
+ gArmTokenSpaceGuid.PcdArmPrimaryCore\r
+\r
+[Depex]\r
+ gEfiCpuArchProtocolGuid\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmGicLib\r
+ FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmGicLib\r
+\r
+[Sources]\r
+ ArmGic.c\r
+ ArmGicNonSec.c\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ MdePkg/MdePkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{ \r
+ /*\r
+ * Enable the CPU interface in Non-Secure world\r
+ * Note: The ICCICR register is banked when Security extensions are implemented\r
+ */\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableDistributor (\r
+ IN INTN GicDistributorBase\r
+ )\r
+{\r
+ /*\r
+ * Enable GIC distributor in Non-Secure world.\r
+ * Note: The ICDDCR register is banked when Security extensions are implemented\r
+ */\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);\r
+}\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/ArmPlatformLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+/*\r
+ * This function configures the all interrupts to be Non-secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetupNonSecure (\r
+ IN UINTN MpId,\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ UINTN InterruptId;\r
+ UINTN CachedPriorityMask;\r
+ UINTN Index;\r
+\r
+ CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
+\r
+ // Set priority Mask so that no interrupts get through to CPU\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
+\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+\r
+ // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+ while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+\r
+ // Next\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+ }\r
+\r
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
+ if (ArmPlatformIsPrimaryCore (MpId)) {\r
+ // Ensure all GIC interrupts are Non-Secure\r
+ for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
+ }\r
+ } else {\r
+ // The secondary cores only set the Non Secure bit to their banked PPIs\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
+ }\r
+\r
+ // Ensure all interrupts can get through the priority mask\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
+}\r
+\r
+/*\r
+ * This function configures the interrupts set by the mask to be secure.\r
+ *\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmGicSetSecureInterrupts (\r
+ IN UINTN GicDistributorBase,\r
+ IN UINTN* GicSecureInterruptMask,\r
+ IN UINTN GicSecureInterruptMaskSize\r
+ )\r
+{\r
+ UINTN Index;\r
+ UINT32 InterruptStatus;\r
+\r
+ // We must not have more interrupts defined by the mask than the number of available interrupts\r
+ ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
+\r
+ // Set all the interrupts defined by the mask as Secure\r
+ for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
+ InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
+ }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ // Set Priority Mask to allow interrupts\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
+\r
+ // Enable CPU interface in Secure world\r
+ // Enable CPU interface in Non-secure World\r
+ // Signal Secure Interrupts to CPU using FIQ line *\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+ ARM_GIC_ICCICR_ENABLE_SECURE |\r
+ ARM_GIC_ICCICR_ENABLE_NS |\r
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ UINT32 ControlValue;\r
+\r
+ // Disable CPU interface in Secure world and Non-secure World\r
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableDistributor (\r
+ IN INTN GicDistributorBase\r
+ )\r
+{\r
+ // Turn on the GIC distributor\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ArmGicSecLib\r
+ FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmGicLib\r
+\r
+[Sources]\r
+ ArmGic.c\r
+ ArmGicSec.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmLib\r
+ ArmPlatformLib\r
+ DebugLib\r
+ IoLib\r
+ PcdLib\r
+\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-UINTN\r
-EFIAPI\r
-ArmGicGetMaxNumInterrupts (\r
- IN INTN GicDistributorBase\r
- )\r
-{\r
- return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList,\r
- IN INTN SgiId\r
- )\r
-{\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);\r
-}\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-ArmGicAcknowledgeInterrupt (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN GicInterruptInterfaceBase,\r
- OUT UINTN *CoreId,\r
- OUT UINTN *InterruptId\r
- )\r
-{\r
- UINT32 Interrupt;\r
-\r
- // Read the Interrupt Acknowledge Register\r
- Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-\r
- // Check if it is a valid interrupt ID\r
- if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
- // Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Interrupt);\r
-\r
- if (CoreId) {\r
- *CoreId = (Interrupt >> 10) & 0x7;\r
- }\r
- if (InterruptId) {\r
- *InterruptId = Interrupt & 0x3FF;\r
- }\r
- return RETURN_SUCCESS;\r
- } else {\r
- return RETURN_INVALID_PARAMETER;\r
- }\r
-}\r
+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r
-Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r
-Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR> \r
-\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-Module Name:\r
-\r
- Gic.c\r
-\r
-Abstract:\r
-\r
- Driver implementing the GIC interrupt controller protocol\r
-\r
---*/\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-#include <Protocol/Cpu.h>\r
-#include <Protocol/HardwareInterrupt.h>\r
-\r
-#define ARM_GIC_DEFAULT_PRIORITY 0x80\r
-\r
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;\r
-\r
-//\r
-// Notifications\r
-//\r
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
-\r
-// Maximum Number of Interrupts\r
-UINTN mGicNumInterrupts = 0;\r
-\r
-HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;\r
-\r
-/**\r
- Register Handler for the specified interrupt source.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
- @param Handler Callback for interrupt. NULL to unregister\r
-\r
- @retval EFI_SUCCESS Source was updated to support Handler.\r
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-RegisterInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN HARDWARE_INTERRUPT_HANDLER Handler\r
- )\r
-{\r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
- \r
- if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
- return EFI_INVALID_PARAMETER;\r
- }\r
-\r
- if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
- return EFI_ALREADY_STARTED;\r
- }\r
-\r
- gRegisteredInterruptHandlers[Source] = Handler;\r
-\r
- // If the interrupt handler is unregistered then disable the interrupt\r
- if (NULL == Handler){\r
- return This->DisableInterruptSource (This, Source);\r
- } else {\r
- return This->EnableInterruptSource (This, Source);\r
- }\r
-}\r
-\r
-/**\r
- Enable interrupt source Source.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
-\r
- @retval EFI_SUCCESS Source interrupt enabled.\r
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-EnableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
- )\r
-{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
- \r
- // Calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
-\r
- // Write set-enable register\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);\r
- \r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Disable interrupt source Source.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
-\r
- @retval EFI_SUCCESS Source interrupt disabled.\r
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-DisableInterruptSource (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
- )\r
-{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
- \r
- // Calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
-\r
- // Write set-enable register\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);\r
- \r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Return current state of interrupt source Source.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
- @param InterruptState TRUE: source enabled, FALSE: source disabled.\r
-\r
- @retval EFI_SUCCESS InterruptState is valid\r
- @retval EFI_DEVICE_ERROR InterruptState is not valid\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-GetInterruptSourceState (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source,\r
- IN BOOLEAN *InterruptState\r
- )\r
-{\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- \r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
- \r
- // calculate enable register offset and bit position\r
- RegOffset = Source / 32;\r
- RegShift = Source % 32;\r
- \r
- if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {\r
- *InterruptState = FALSE;\r
- } else {\r
- *InterruptState = TRUE;\r
- }\r
- \r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Signal to the hardware that the End Of Intrrupt state \r
- has been reached.\r
-\r
- @param This Instance pointer for this protocol\r
- @param Source Hardware source of the interrupt\r
-\r
- @retval EFI_SUCCESS Source interrupt EOI'ed.\r
- @retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-EndOfInterrupt (\r
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
- IN HARDWARE_INTERRUPT_SOURCE Source\r
- )\r
-{\r
- if (Source > mGicNumInterrupts) {\r
- ASSERT(FALSE);\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
-\r
- @param InterruptType Defines the type of interrupt or exception that\r
- occurred on the processor.This parameter is processor architecture specific.\r
- @param SystemContext A pointer to the processor context when\r
- the interrupt occurred on the processor.\r
-\r
- @return None\r
-\r
-**/\r
-VOID\r
-EFIAPI\r
-IrqInterruptHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
- )\r
-{\r
- UINT32 GicInterrupt;\r
- HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
-\r
- GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);\r
-\r
- // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
- if (GicInterrupt >= mGicNumInterrupts) {\r
- // The special interrupt do not need to be acknowledge\r
- return;\r
- }\r
- \r
- InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];\r
- if (InterruptHandler != NULL) {\r
- // Call the registered interrupt handler.\r
- InterruptHandler (GicInterrupt, SystemContext);\r
- } else {\r
- DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));\r
- }\r
-\r
- EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);\r
-}\r
-\r
-//\r
-// Making this global saves a few bytes in image size\r
-//\r
-EFI_HANDLE gHardwareInterruptHandle = NULL;\r
-\r
-//\r
-// The protocol instance produced by this driver\r
-//\r
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
- RegisterInterruptSource,\r
- EnableInterruptSource,\r
- DisableInterruptSource,\r
- GetInterruptSourceState,\r
- EndOfInterrupt\r
-};\r
-\r
-/**\r
- Shutdown our hardware\r
- \r
- DXE Core will disable interrupts and turn off the timer and disable interrupts\r
- after all the event handlers have run.\r
-\r
- @param[in] Event The Event that is being processed\r
- @param[in] Context Event Context\r
-**/\r
-VOID\r
-EFIAPI\r
-ExitBootServicesEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
- )\r
-{\r
- UINTN Index;\r
- \r
- // Acknowledge all pending interrupts\r
- for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
- DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
- }\r
-\r
- for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
- EndOfInterrupt (&gHardwareInterruptProtocol, Index);\r
- }\r
-\r
- // Disable Gic Interface\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);\r
-\r
- // Disable Gic Distributor\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);\r
-}\r
-\r
-/**\r
- Initialize the state information for the CPU Architectural Protocol\r
-\r
- @param ImageHandle of the loaded driver\r
- @param SystemTable Pointer to the System Table\r
-\r
- @retval EFI_SUCCESS Protocol registered\r
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
- @retval EFI_DEVICE_ERROR Hardware problems\r
-\r
-**/\r
-EFI_STATUS\r
-InterruptDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINT32 RegOffset;\r
- UINTN RegShift;\r
- EFI_CPU_ARCH_PROTOCOL *Cpu;\r
- UINT32 CpuTarget;\r
- \r
- // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
-\r
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));\r
-\r
- for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
- DisableInterruptSource (&gHardwareInterruptProtocol, Index);\r
- \r
- // Set Priority \r
- RegOffset = Index / 4;\r
- RegShift = (Index % 4) * 8;\r
- MmioAndThenOr32 (\r
- PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),\r
- ~(0xff << RegShift), \r
- ARM_GIC_DEFAULT_PRIORITY << RegShift\r
- );\r
- }\r
-\r
- //\r
- // Targets the interrupts to the Primary Cpu\r
- //\r
-\r
- // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
- // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
- // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
- // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
- //\r
- // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
- // first SGIs)\r
- CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
-\r
- // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
- // is 0 when we run on a uniprocessor platform.\r
- if (CpuTarget != 0) {\r
- // The 8 first Interrupt Processor Targets Registers are read-only\r
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
- }\r
- }\r
-\r
- // Set binary point reg to 0x7 (no preemption)\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);\r
-\r
- // Set priority mask reg to 0xff to allow all priorities through\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
- \r
- // Enable gic cpu interface\r
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);\r
-\r
- // Enable gic distributor\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);\r
- \r
- // Initialize the array for the Interrupt Handlers\r
- gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);\r
- \r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &gHardwareInterruptHandle,\r
- &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- \r
- //\r
- // Get the CPU protocol that this driver requires.\r
- //\r
- Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Unregister the default exception handler.\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- //\r
- // Register to receive interrupts\r
- //\r
- Status = Cpu->RegisterInterruptHandler(Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);\r
- ASSERT_EFI_ERROR(Status);\r
-\r
- // Register for an ExitBootServicesEvent\r
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return Status;\r
-}\r
+++ /dev/null
-#/** @file\r
-# \r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# \r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL390GicDxe\r
- FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 \r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
-\r
- ENTRY_POINT = InterruptDxeInitialize\r
-\r
-\r
-[Sources.common]\r
- PL390Gic.c\r
- PL390GicDxe.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
-\r
-[LibraryClasses]\r
- BaseLib\r
- UefiLib\r
- UefiBootServicesTableLib\r
- DebugLib\r
- PrintLib\r
- MemoryAllocationLib\r
- UefiDriverEntryPoint\r
- IoLib\r
-\r
-[Protocols]\r
- gHardwareInterruptProtocolGuid\r
- gEfiCpuArchProtocolGuid\r
- \r
-[FixedPcd.common]\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
- \r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
-[Depex]\r
- gEfiCpuArchProtocolGuid\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL390GicLib\r
- FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmGicLib\r
-\r
-[Sources]\r
- PL390Gic.c\r
- PL390GicNonSec.c\r
-\r
-[LibraryClasses]\r
- IoLib\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Uefi.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{ \r
- /*\r
- * Enable the CPU interface in Non-Secure world\r
- * Note: The ICCICR register is banked when Security extensions are implemented\r
- */\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableDistributor (\r
- IN INTN GicDistributorBase\r
- )\r
-{\r
- /*\r
- * Enable GIC distributor in Non-Secure world.\r
- * Note: The ICDDCR register is banked when Security extensions are implemented\r
- */\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-\r
-/*\r
- * This function configures the all interrupts to be Non-secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicSetupNonSecure (\r
- IN UINTN MpId,\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{\r
- UINTN InterruptId;\r
- UINTN CachedPriorityMask;\r
- UINTN Index;\r
-\r
- CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
-\r
- // Set priority Mask so that no interrupts get through to CPU\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
-\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
-\r
- // Only try to clear valid interrupts. Ignore spurious interrupts.\r
- while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
-\r
- // Next\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
- }\r
-\r
- // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- // Ensure all GIC interrupts are Non-Secure\r
- for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
- }\r
- } else {\r
- // The secondary cores only set the Non Secure bit to their banked PPIs\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);\r
- }\r
-\r
- // Ensure all interrupts can get through the priority mask\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
-}\r
-\r
-/*\r
- * This function configures the interrupts set by the mask to be secure.\r
- *\r
- */\r
-VOID\r
-EFIAPI\r
-ArmGicSetSecureInterrupts (\r
- IN UINTN GicDistributorBase,\r
- IN UINTN* GicSecureInterruptMask,\r
- IN UINTN GicSecureInterruptMaskSize\r
- )\r
-{\r
- UINTN Index;\r
- UINT32 InterruptStatus;\r
-\r
- // We must not have more interrupts defined by the mask than the number of available interrupts\r
- ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
-\r
- // Set all the interrupts defined by the mask as Secure\r
- for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r
- InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));\r
- }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{\r
- // Set Priority Mask to allow interrupts\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);\r
-\r
- // Enable CPU interface in Secure world\r
- // Enable CPU interface in Non-secure World\r
- // Signal Secure Interrupts to CPU using FIQ line *\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
- ARM_GIC_ICCICR_ENABLE_SECURE |\r
- ARM_GIC_ICCICR_ENABLE_NS |\r
- ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicDisableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- )\r
-{\r
- UINT32 ControlValue;\r
-\r
- // Disable CPU interface in Secure world and Non-secure World\r
- ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
- MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmGicEnableDistributor (\r
- IN INTN GicDistributorBase\r
- )\r
-{\r
- // Turn on the GIC distributor\r
- MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL390GicSecLib\r
- FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmGicLib\r
-\r
-[Sources]\r
- PL390Gic.c\r
- PL390GicSec.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
-\r
-[LibraryClasses]\r
- ArmLib\r
- ArmPlatformLib\r
- DebugLib\r
- IoLib\r
- PcdLib\r
-\r
*\r
**/\r
\r
-#ifndef __PL390GIC_H\r
-#define __PL390GIC_H\r
+#ifndef __ARMGIC_H\r
+#define __ARMGIC_H\r
\r
//\r
// GIC definitions\r
CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
\r
CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
\r
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x10041000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x10040000\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x1F001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1F000100\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
\r
# RealView Emulation Board Specific Libraries\r
\r
#DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
\r
- # ARM PL390 General Interrupt Driver in Secure and Non-secure\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ # ARM General Interrupt Driver in Secure and Non-secure\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
\r
LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf\r
\r
\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
#ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
#INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x1e001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1e000100\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
\r
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000100\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
\r
gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
\r
#\r
- # ARM PL390 General Interrupt Controller\r
+ # ARM General Interrupt Controller\r
#\r
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
ArmPlatformPkg/Sec/Sec.inf {\r
<LibraryClasses>\r
# Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
}\r
\r
#\r
\r
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
\r
- ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
INF EmbeddedPkg/SerialDxe/SerialDxe.inf\r
\r
- INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf\r
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf\r
ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf\r
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf\r
- ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf\r
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
\r
projects / mirror_edk2.git / commitdiff