UefiCpuPkg/ExceptionLib: Conditionally clear shadow stack token busy bit

When enter SMM exception, there will be a stack switch only if the IST
field of the interrupt gate is set. When CET shadow stack feature is
enabled, if there is a stack switch between SMM exception and SMM, the
shadow stack token busy bit needs to be cleared when return from SMM
exception to SMM. In UEFI BIOS, only page fault exception does the stack
swith when SMM shack guard feature is enabled. The condition of clear
shadow stack token busy bit should be SMM stack guard enabled, CET shadows
stack feature enabled and page fault exception.
The shadow stack token should be initialized by UINT64.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3462

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Qihua Zhuang <qihua.zhuang@intel.com>
Cc: Daquan Dong <daquan.dong@intel.com>
Cc: Justin Tong <justin.tong@intel.com>
Cc: Tom Xu <tom.xu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
index ebe0eec874c3dd3d4ec80c4bc74b08496cbc966d..4881a02848f3d8efc1e272f74bb07b98ba21de99 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
@@ -20,6 +20,7 @@
 ;\r
 \r
 %define VC_EXCEPTION 29\r
+%define PF_EXCEPTION 14\r
 \r
 extern ASM_PFX(mErrorCodeFlag)    ; Error code flags for exceptions\r
 extern ASM_PFX(mDoFarReturnFlag)  ; Do far return flag\r
@@ -279,6 +280,46 @@ DrFinish:
     call    ASM_PFX(CommonExceptionHandler)\r
     add     rsp, 4 * 8 + 8\r
 \r
+    ; The follow algorithm is used for clear shadow stack token busy bit.\r
+    ; The comment is based on the sample shadow stack.\r
+    ; The sample shadow stack layout :\r
+    ; Address | Context\r
+    ;         +-------------------------+\r
+    ;  0xFD0  |   FREE                  | it is 0xFD8|0x02|(LMA & CS.L), after SAVEPREVSSP.\r
+    ;         +-------------------------+\r
+    ;  0xFD8  |  Prev SSP               |\r
+    ;         +-------------------------+\r
+    ;  0xFE0  |   RIP                   |\r
+    ;         +-------------------------+\r
+    ;  0xFE8  |   CS                    |\r
+    ;         +-------------------------+\r
+    ;  0xFF0  |  0xFF0 | BUSY           | BUSY flag cleared after CLRSSBSY\r
+    ;         +-------------------------+\r
+    ;  0xFF8  | 0xFD8|0x02|(LMA & CS.L) |\r
+    ;         +-------------------------+\r
+    ; Instructions for Intel Control Flow Enforcement Technology (CET) are supported since NASM version 2.15.01.\r
+    cmp     qword [ASM_PFX(mDoFarReturnFlag)], 0\r
+    jz      CetDone\r
+    cmp     qword [rbp + 8], PF_EXCEPTION   ; check if it is a Page Fault\r
+    jnz     CetDone\r
+    cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
+    jz      CetDone\r
+    mov     rax, cr4\r
+    and     rax, 0x800000       ; check if CET is enabled\r
+    jz      CetDone\r
+                                ; SSP should be 0xFD8 at this point\r
+    mov     rax, 0x04           ; advance past cs:lip:prevssp;supervisor shadow stack token\r
+    INCSSP_RAX                  ; After this SSP should be 0xFF8\r
+    SAVEPREVSSP                 ; now the shadow stack restore token will be created at 0xFD0\r
+    READSSP_RAX                 ; Read new SSP, SSP should be 0x1000\r
+    sub     rax, 0x10\r
+    CLRSSBSY_RAX                ; Clear token at 0xFF0, SSP should be 0 after this\r
+    sub     rax, 0x20\r
+    RSTORSSP_RAX                ; Restore to token at 0xFD0, new SSP will be 0xFD0\r
+    mov     rax, 0x01           ; Pop off the new save token created\r
+    INCSSP_RAX                  ; SSP should be 0xFD8 now\r
+CetDone:\r
+\r
     cli\r
 ;; UINT64  ExceptionData;\r
     add     rsp, 8\r
@@ -373,47 +414,7 @@ DoReturn:
     push    qword [rax + 0x18]       ; save EFLAGS in new location\r
     mov     rax, [rax]        ; restore rax\r
     popfq                     ; restore EFLAGS\r
-\r
-    ; The follow algorithm is used for clear shadow stack token busy bit.\r
-    ; The comment is based on the sample shadow stack.\r
-    ; The sample shadow stack layout :\r
-    ; Address | Context\r
-    ;         +-------------------------+\r
-    ;  0xFD0  |   FREE                  | it is 0xFD8|0x02|(LMA & CS.L), after SAVEPREVSSP.\r
-    ;         +-------------------------+\r
-    ;  0xFD8  |  Prev SSP               |\r
-    ;         +-------------------------+\r
-    ;  0xFE0  |   RIP                   |\r
-    ;         +-------------------------+\r
-    ;  0xFE8  |   CS                    |\r
-    ;         +-------------------------+\r
-    ;  0xFF0  |  0xFF0 | BUSY           | BUSY flag cleared after CLRSSBSY\r
-    ;         +-------------------------+\r
-    ;  0xFF8  | 0xFD8|0x02|(LMA & CS.L) |\r
-    ;         +-------------------------+\r
-    ; Instructions for Intel Control Flow Enforcement Technology (CET) are supported since NASM version 2.15.01.\r
-    push     rax                ; SSP should be 0xFD8 at this point\r
-    cmp      byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
-    jz       CetDone\r
-    mov      rax, cr4\r
-    and      rax, 0x800000      ; check if CET is enabled\r
-    jz       CetDone\r
-    mov      rax, 0x04          ; advance past cs:lip:prevssp;supervisor shadow stack token\r
-    INCSSP_RAX                  ; After this SSP should be 0xFF8\r
-    SAVEPREVSSP                 ; now the shadow stack restore token will be created at 0xFD0\r
-    READSSP_RAX                 ; Read new SSP, SSP should be 0x1000\r
-    push     rax\r
-    sub      rax, 0x10\r
-    CLRSSBSY_RAX                ; Clear token at 0xFF0, SSP should be 0 after this\r
-    sub      rax, 0x20\r
-    RSTORSSP_RAX                ; Restore to token at 0xFD0, new SSP will be 0xFD0\r
-    pop      rax\r
-    mov      rax, 0x01          ; Pop off the new save token created\r
-    INCSSP_RAX                  ; SSP should be 0xFD8 now\r
-CetDone:\r
-    pop      rax                ; restore rax\r
-\r
-    DB       0x48               ; prefix to composite "retq" with next "retf"\r
+    DB      0x48                ; prefix to composite "retq" with next "retf"\r
     retf                        ; far return\r
 DoIret:\r
     iretq\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index 661c1ba2948df809c9ce950d4f6d97f38fa386df..ca3f5ff91a0bac83bd6fcff9a6248875c7a75627 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -202,7 +202,7 @@ InitShadowStack (
       // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.\r
       //\r
       InterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));\r
-      *(UINT32 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;\r
+      *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;\r
       mCetInterruptSsp = InterruptSsp - sizeof(UINT64);\r
 \r
       mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);\r